ATE485597T1 - Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen - Google Patents

Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen

Info

Publication number
ATE485597T1
ATE485597T1 AT08789258T AT08789258T ATE485597T1 AT E485597 T1 ATE485597 T1 AT E485597T1 AT 08789258 T AT08789258 T AT 08789258T AT 08789258 T AT08789258 T AT 08789258T AT E485597 T1 ATE485597 T1 AT E485597T1
Authority
AT
Austria
Prior art keywords
integrated circuits
wafer
producing
pick
circuits
Prior art date
Application number
AT08789258T
Other languages
English (en)
Inventor
Heimo Scheucher
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE485597T1 publication Critical patent/ATE485597T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
AT08789258T 2007-07-12 2008-07-10 Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen ATE485597T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07112371 2007-07-12
PCT/IB2008/052778 WO2009007929A2 (en) 2007-07-12 2008-07-10 Integrated circuits on a wafer and methods for manufacturing integrated circuits

Publications (1)

Publication Number Publication Date
ATE485597T1 true ATE485597T1 (de) 2010-11-15

Family

ID=40229191

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08789258T ATE485597T1 (de) 2007-07-12 2008-07-10 Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen

Country Status (6)

Country Link
US (1) US9620456B2 (de)
EP (1) EP2168156B1 (de)
CN (1) CN101689541B (de)
AT (1) ATE485597T1 (de)
DE (1) DE602008003128D1 (de)
WO (1) WO2009007929A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009007932A2 (en) * 2007-07-12 2009-01-15 Nxp B.V. Integrated circuits on a wafer and method of producing integrated circuits
US9798228B2 (en) * 2015-09-29 2017-10-24 Nxp B.V. Maximizing potential good die per wafer, PGDW
US10942444B2 (en) * 2019-05-01 2021-03-09 Nxp Usa, Inc. Optical control modules for integrated circuit device patterning and reticles and methods including the same
CN110271723A (zh) * 2019-07-04 2019-09-24 宁波市鄞州特尔斐电子有限公司 一种集成电路撕膜机的自动撕膜装置

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3696352B2 (ja) 1996-12-17 2005-09-14 三菱電機株式会社 ライフタイム評価用ｔｅｇ
US6133582A (en) * 1998-05-14 2000-10-17 Lightspeed Semiconductor Corporation Methods and apparatuses for binning partially completed integrated circuits based upon test results
JP3758366B2 (ja) * 1998-05-20 2006-03-22 富士通株式会社 半導体装置
US6713955B1 (en) * 1998-11-20 2004-03-30 Agilent Technologies, Inc. Organic light emitting device having a current self-limiting structure
JP4299420B2 (ja) 1999-11-09 2009-07-22 川崎マイクロエレクトロニクス株式会社 逐次露光方法
JP4271939B2 (ja) 2001-02-27 2009-06-03 エヌエックスピー ビー ヴィ プロセス制御モジュールを有する半導体ウェハ
JP3711341B2 (ja) 2001-04-27 2005-11-02 沖電気工業株式会社 半導体装置
JP3872319B2 (ja) 2001-08-21 2007-01-24 沖電気工業株式会社 半導体装置及びその製造方法
EP1563537B1 (de) 2002-11-08 2008-04-09 Nxp B.V. Integrierte Schaltung mit mindestens einem Kontakthöcker
CN1898607A (zh) 2003-12-23 2007-01-17 皇家飞利浦电子股份有限公司 在曝光场中具有光学控制模块的晶片
US7456489B2 (en) * 2003-12-23 2008-11-25 Nxp B.V. Wafer with optical control modules in IC fields
CN100481438C (zh) 2003-12-23 2009-04-22 Nxp股份有限公司 划片路径中具有光学控制模块的晶片
US7193296B2 (en) * 2004-01-26 2007-03-20 Yamaha Corporation Semiconductor substrate
ATE541312T1 (de) 2004-05-28 2012-01-15 Nxp Bv Chip mit zwei gruppen von chipkontakten
WO2005117115A1 (en) 2004-05-28 2005-12-08 Koninklijke Philips Electronics N.V. Chips with useful lines and dummy lines
US7239163B1 (en) * 2004-06-23 2007-07-03 Ridgetop Group, Inc. Die-level process monitor and method
JP2006030318A (ja) * 2004-07-12 2006-02-02 Sanyo Electric Co Ltd 表示装置
US7223673B2 (en) * 2004-07-15 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device with crack prevention ring
JP2006038987A (ja) * 2004-07-23 2006-02-09 Seiko Epson Corp 表示装置、表示装置の製造方法、電子機器
EP1774587B1 (de) 2004-07-26 2009-10-07 Nxp B.V. Wafer mit verbesserten leitenden schleifen im ritzrahmen
EP1790008A1 (de) 2004-08-31 2007-05-30 Koninklijke Philips Electronics N.V. Chip mit mindestens einer testkontaktkonfiguration
FR2884045A1 (fr) 2005-03-29 2006-10-06 St Microelectronics Sa Identification d'un circuit integre de reference pour equipement de prise et pose
WO2006132165A1 (ja) 2005-06-06 2006-12-14 Toray Industries, Inc. 半導体用接着組成物、それを用いた半導体装置および半導体装置の製造方法
US7295642B2 (en) 2005-06-30 2007-11-13 Teradyne, Inc. Jitter compensation and generation in testing communication devices
JP2007067372A (ja) 2005-08-03 2007-03-15 Matsushita Electric Ind Co Ltd 半導体装置
JP5201137B2 (ja) * 2007-01-22 2013-06-05 パナソニック株式会社 高分子抵抗体
US20080290340A1 (en) * 2007-05-23 2008-11-27 Texas Instruments Incorporated Method for fabricating a semiconductor device having embedded interconnect structures to improve die corner robustness

Also Published As

Publication number Publication date
EP2168156B1 (de) 2010-10-20
US20100140748A1 (en) 2010-06-10
CN101689541A (zh) 2010-03-31
US9620456B2 (en) 2017-04-11
DE602008003128D1 (de) 2010-12-02
WO2009007929A3 (en) 2009-04-02
WO2009007929A2 (en) 2009-01-15
CN101689541B (zh) 2012-01-25
EP2168156A2 (de) 2010-03-31

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