ATE492028T1 - Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird - Google Patents

Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird

Info

Publication number
ATE492028T1
ATE492028T1 AT03763892T AT03763892T ATE492028T1 AT E492028 T1 ATE492028 T1 AT E492028T1 AT 03763892 T AT03763892 T AT 03763892T AT 03763892 T AT03763892 T AT 03763892T AT E492028 T1 ATE492028 T1 AT E492028T1
Authority
AT
Austria
Prior art keywords
substrate
outline
support
useful layer
chamfer
Prior art date
Application number
AT03763892T
Other languages
English (en)
Inventor
Christophe Maleville
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Priority claimed from PCT/EP2003/007855 external-priority patent/WO2004008527A1/en
Application granted granted Critical
Publication of ATE492028T1 publication Critical patent/ATE492028T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1924—Preparing SOI wafers with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/15—Sheet, web, or layer weakened to permit separation through thickness
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/21—Circular sheet or circular blank
    • Y10T428/219—Edge structure

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Silicon Compounds (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
AT03763892T 2002-07-17 2003-07-16 Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird ATE492028T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0209017A FR2842646B1 (fr) 2002-07-17 2002-07-17 Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support
US46899003P 2003-05-09 2003-05-09
PCT/EP2003/007855 WO2004008527A1 (en) 2002-07-17 2003-07-16 A method of increasing the area of a useful layer of material transferred onto a support

Publications (1)

Publication Number Publication Date
ATE492028T1 true ATE492028T1 (de) 2011-01-15

Family

ID=29797482

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03763892T ATE492028T1 (de) 2002-07-17 2003-07-16 Verfahren zur vergrösserung der fläche einer nützlichen materialschicht, die auf einen träger übertragen wird

Country Status (4)

Country Link
US (2) US7048867B2 (de)
AT (1) ATE492028T1 (de)
DE (1) DE60335388D1 (de)
FR (1) FR2842646B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2842649B1 (fr) * 2002-07-17 2005-06-24 Soitec Silicon On Insulator Procede d'augmentation de l'aire d'une couche utile de materiau reportee sur un support
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
JP4525353B2 (ja) * 2005-01-07 2010-08-18 住友電気工業株式会社 Ｉｉｉ族窒化物基板の製造方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8440541B2 (en) * 2010-02-25 2013-05-14 Memc Electronic Materials, Inc. Methods for reducing the width of the unbonded region in SOI structures
US9156705B2 (en) 2010-12-23 2015-10-13 Sunedison, Inc. Production of polycrystalline silicon by the thermal decomposition of dichlorosilane in a fluidized bed reactor
FR3074608B1 (fr) * 2017-12-05 2019-12-06 Soitec Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2825048B2 (ja) 1992-08-10 1998-11-18 信越半導体株式会社 半導体シリコン基板
US5597410A (en) * 1994-09-15 1997-01-28 Yen; Yung C. Method to make a SOI wafer for IC manufacturing
US6113721A (en) * 1995-01-03 2000-09-05 Motorola, Inc. Method of bonding a semiconductor wafer
JPH1093122A (ja) 1996-09-10 1998-04-10 Nippon Telegr & Teleph Corp <Ntt> 薄膜太陽電池の製造方法
FR2774510B1 (fr) * 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
US6664169B1 (en) * 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
WO2001073831A1 (fr) * 2000-03-29 2001-10-04 Shin-Etsu Handotai Co., Ltd. Procede d'obtention de tranches de silicium ou de soi et tranches ainsi obtenues
JP4846915B2 (ja) 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
JP2001284622A (ja) 2000-03-31 2001-10-12 Canon Inc 半導体部材の製造方法及び太陽電池の製造方法
JP4628580B2 (ja) * 2001-04-18 2011-02-09 信越半導体株式会社 貼り合せ基板の製造方法
US20040224482A1 (en) * 2001-12-20 2004-11-11 Kub Francis J. Method for transferring thin film layer material to a flexible substrate using a hydrogen ion splitting technique

Also Published As

Publication number Publication date
US20040081790A1 (en) 2004-04-29
US7452584B2 (en) 2008-11-18
DE60335388D1 (de) 2011-01-27
FR2842646A1 (fr) 2004-01-23
US20060124584A1 (en) 2006-06-15
FR2842646B1 (fr) 2005-06-24
US7048867B2 (en) 2006-05-23

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Legal Events

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