ATE492943T1 - Aktivabschlussschaltung und verfahren zur steuerung der impedanz integrierter abschlüsse von integrierten schaltungen - Google Patents
Aktivabschlussschaltung und verfahren zur steuerung der impedanz integrierter abschlüsse von integrierten schaltungenInfo
- Publication number
- ATE492943T1 ATE492943T1 AT02789818T AT02789818T ATE492943T1 AT E492943 T1 ATE492943 T1 AT E492943T1 AT 02789818 T AT02789818 T AT 02789818T AT 02789818 T AT02789818 T AT 02789818T AT E492943 T1 ATE492943 T1 AT E492943T1
- Authority
- AT
- Austria
- Prior art keywords
- impedance
- integrated
- control signal
- termination circuit
- controlling
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Networks Using Active Elements (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/997,156 US6657906B2 (en) | 2001-11-28 | 2001-11-28 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals |
| PCT/US2002/037454 WO2003047104A1 (en) | 2001-11-28 | 2002-11-20 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE492943T1 true ATE492943T1 (de) | 2011-01-15 |
Family
ID=25543703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT02789818T ATE492943T1 (de) | 2001-11-28 | 2002-11-20 | Aktivabschlussschaltung und verfahren zur steuerung der impedanz integrierter abschlüsse von integrierten schaltungen |
Country Status (9)
| Country | Link |
|---|---|
| US (8) | US6657906B2 (de) |
| EP (1) | EP1461862B1 (de) |
| KR (1) | KR100884226B1 (de) |
| CN (1) | CN100407577C (de) |
| AT (1) | ATE492943T1 (de) |
| AU (1) | AU2002352860A1 (de) |
| DE (1) | DE60238713D1 (de) |
| TW (1) | TWI288527B (de) |
| WO (1) | WO2003047104A1 (de) |
Families Citing this family (66)
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-
2001
- 2001-11-28 US US09/997,156 patent/US6657906B2/en not_active Expired - Fee Related
-
2002
- 2002-11-19 TW TW091133709A patent/TWI288527B/zh not_active IP Right Cessation
- 2002-11-20 AT AT02789818T patent/ATE492943T1/de not_active IP Right Cessation
- 2002-11-20 EP EP02789818A patent/EP1461862B1/de not_active Expired - Lifetime
- 2002-11-20 DE DE60238713T patent/DE60238713D1/de not_active Expired - Lifetime
- 2002-11-20 AU AU2002352860A patent/AU2002352860A1/en not_active Abandoned
- 2002-11-20 WO PCT/US2002/037454 patent/WO2003047104A1/en not_active Ceased
- 2002-11-20 KR KR1020047008892A patent/KR100884226B1/ko not_active Expired - Fee Related
- 2002-11-20 CN CN028276124A patent/CN100407577C/zh not_active Expired - Fee Related
-
2003
- 2003-02-26 US US10/375,639 patent/US6711073B2/en not_active Expired - Fee Related
-
2004
- 2004-01-21 US US10/762,605 patent/US6944071B2/en not_active Expired - Fee Related
- 2004-11-29 US US10/999,771 patent/US7106638B2/en not_active Expired - Fee Related
- 2004-11-29 US US10/999,770 patent/US7187601B2/en not_active Expired - Fee Related
-
2006
- 2006-01-10 US US11/329,596 patent/US7715256B2/en not_active Expired - Fee Related
- 2006-01-10 US US11/329,482 patent/US7382667B2/en not_active Expired - Fee Related
-
2010
- 2010-04-15 US US12/760,841 patent/US8054703B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1618169A (zh) | 2005-05-18 |
| TWI288527B (en) | 2007-10-11 |
| US7187601B2 (en) | 2007-03-06 |
| US6657906B2 (en) | 2003-12-02 |
| KR100884226B1 (ko) | 2009-02-17 |
| US7382667B2 (en) | 2008-06-03 |
| US8054703B2 (en) | 2011-11-08 |
| EP1461862A1 (de) | 2004-09-29 |
| EP1461862A4 (de) | 2007-12-05 |
| TW200301615A (en) | 2003-07-01 |
| US20060109722A1 (en) | 2006-05-25 |
| US20040184326A1 (en) | 2004-09-23 |
| US7715256B2 (en) | 2010-05-11 |
| WO2003047104A1 (en) | 2003-06-05 |
| AU2002352860A1 (en) | 2003-06-10 |
| US20050094444A1 (en) | 2005-05-05 |
| US20060109723A1 (en) | 2006-05-25 |
| US7106638B2 (en) | 2006-09-12 |
| US20050094468A1 (en) | 2005-05-05 |
| US6944071B2 (en) | 2005-09-13 |
| KR20040080433A (ko) | 2004-09-18 |
| US20030099137A1 (en) | 2003-05-29 |
| US20100220537A1 (en) | 2010-09-02 |
| EP1461862B1 (de) | 2010-12-22 |
| US20030128599A1 (en) | 2003-07-10 |
| DE60238713D1 (de) | 2011-02-03 |
| US6711073B2 (en) | 2004-03-23 |
| CN100407577C (zh) | 2008-07-30 |
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| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |