ATE498904T1 - Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers - Google Patents

Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers

Info

Publication number
ATE498904T1
ATE498904T1 AT03789586T AT03789586T ATE498904T1 AT E498904 T1 ATE498904 T1 AT E498904T1 AT 03789586 T AT03789586 T AT 03789586T AT 03789586 T AT03789586 T AT 03789586T AT E498904 T1 ATE498904 T1 AT E498904T1
Authority
AT
Austria
Prior art keywords
semiconductor wafer
atmosphere
improving
surface roughness
purged
Prior art date
Application number
AT03789586T
Other languages
English (en)
Inventor
Eric Neyret
Emmanuel Arene
Ludovic Ecarnot
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE498904T1 publication Critical patent/ATE498904T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/906—Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15—Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Formation Of Insulating Films (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Weting (AREA)
AT03789586T 2003-12-03 2003-12-03 Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers ATE498904T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2003/006380 WO2005055308A1 (en) 2003-12-03 2003-12-03 Process for improving the surface roughness of a wafer

Publications (1)

Publication Number Publication Date
ATE498904T1 true ATE498904T1 (de) 2011-03-15

Family

ID=34640309

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03789586T ATE498904T1 (de) 2003-12-03 2003-12-03 Verfahren zur verbesserung der öberflächenrauhigkeit eines halbleiterwafers

Country Status (7)

Country Link
EP (1) EP1690289B9 (de)
JP (1) JP4619949B2 (de)
CN (1) CN1879204B (de)
AT (1) ATE498904T1 (de)
AU (1) AU2003294166A1 (de)
DE (1) DE60336090D1 (de)
WO (1) WO2005055308A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101652835B (zh) * 2007-04-20 2012-03-21 佳能安内华股份有限公司 具有碳化硅基板的半导体器件的退火方法和半导体器件
US9157681B2 (en) 2010-02-04 2015-10-13 National University Corporation Tohoku University Surface treatment method for atomically flattening a silicon wafer and heat treatment apparatus
JPWO2013150636A1 (ja) * 2012-04-05 2015-12-14 国立大学法人東北大学 シリコンウェーハの原子オーダー平坦化表面処理方法及び熱処理装置
EP2835820A1 (de) * 2012-04-05 2015-02-11 National University Corporation, Tohoku University Behandlungsverfahren von atomarer grössenordnung für flache oberflächen eines siliciumwafers und wärmebehandlungsvorrichtung
DE102013018533B4 (de) 2013-08-23 2019-01-10 Centrotherm Photovoltaics Ag Verfahren zum Reduzieren der Oberflächenrauigkeit einer Oberfläche aus Halbleitermaterial eines Substrats mit 3-D Strukturen
CN106920746A (zh) * 2015-12-25 2017-07-04 有研半导体材料有限公司 一种改善硅片表面微缺陷的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192320A (ja) * 1982-05-07 1983-11-09 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JPH07321042A (ja) * 1994-04-19 1995-12-08 Texas Instr Inc <Ti> 集積回路デバイスの製作方法
GB2312525A (en) * 1996-04-24 1997-10-29 Northern Telecom Ltd Providing cladding on planar optical waveguide by heating to flow
JP3478141B2 (ja) * 1998-09-14 2003-12-15 信越半導体株式会社 シリコンウエーハの熱処理方法及びシリコンウエーハ
JP3565068B2 (ja) * 1998-12-28 2004-09-15 信越半導体株式会社 シリコンウエーハの熱処理方法およびシリコンウエーハ
US6573159B1 (en) * 1998-12-28 2003-06-03 Shin-Etsu Handotai Co., Ltd. Method for thermally annealing silicon wafer and silicon wafer
WO2001028000A1 (en) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Method for manufacturing soi wafer, and soi wafer
JP3893608B2 (ja) * 2000-09-21 2007-03-14 信越半導体株式会社 アニールウェーハの製造方法
JP2002110949A (ja) * 2000-09-28 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
JP2002110688A (ja) * 2000-09-29 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US7148570B2 (en) * 2001-08-13 2006-12-12 Sandisk 3D Llc Low resistivity titanium silicide on heavily doped semiconductor
JP5052728B2 (ja) * 2002-03-05 2012-10-17 株式会社Ｓｕｍｃｏ シリコン単結晶層の製造方法
JP4694372B2 (ja) * 2003-12-03 2011-06-08 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ ウェハの表面粗さを改善する方法

Also Published As

Publication number Publication date
EP1690289A1 (de) 2006-08-16
CN1879204A (zh) 2006-12-13
WO2005055308A1 (en) 2005-06-16
CN1879204B (zh) 2010-07-14
EP1690289B9 (de) 2012-03-14
JP4619949B2 (ja) 2011-01-26
EP1690289B1 (de) 2011-02-16
DE60336090D1 (de) 2011-03-31
AU2003294166A1 (en) 2005-06-24
JP2007516586A (ja) 2007-06-21

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