ATE497634T1 - Verfahren zur behandlung eines halbleitenden wafers - Google Patents

Verfahren zur behandlung eines halbleitenden wafers

Info

Publication number
ATE497634T1
ATE497634T1 AT01958558T AT01958558T ATE497634T1 AT E497634 T1 ATE497634 T1 AT E497634T1 AT 01958558 T AT01958558 T AT 01958558T AT 01958558 T AT01958558 T AT 01958558T AT E497634 T1 ATE497634 T1 AT E497634T1
Authority
AT
Austria
Prior art keywords
semiconductor wafer
treating
wafer
semiconducting wafer
sticking
Prior art date
Application number
AT01958558T
Other languages
English (en)
Inventor
Masayuki Yamamoto
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Application granted granted Critical
Publication of ATE497634T1 publication Critical patent/ATE497634T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H10P72/7404—Wafer tapes, e.g. grinding or dicing support tapes the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
AT01958558T 2000-08-30 2001-08-27 Verfahren zur behandlung eines halbleitenden wafers ATE497634T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000260924A JP2002075937A (ja) 2000-08-30 2000-08-30 半導体ウエハの加工方法
PCT/JP2001/007365 WO2002019393A2 (en) 2000-08-30 2001-08-27 Method of processing a semiconductor wafer

Publications (1)

Publication Number Publication Date
ATE497634T1 true ATE497634T1 (de) 2011-02-15

Family

ID=18748861

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01958558T ATE497634T1 (de) 2000-08-30 2001-08-27 Verfahren zur behandlung eines halbleitenden wafers

Country Status (9)

Country Link
US (1) US6803293B2 (de)
EP (1) EP1316111B1 (de)
JP (1) JP2002075937A (de)
KR (1) KR100811958B1 (de)
AT (1) ATE497634T1 (de)
DE (1) DE60143987D1 (de)
PT (1) PT1316111E (de)
TW (1) TW518721B (de)
WO (1) WO2002019393A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003209082A (ja) * 2002-01-15 2003-07-25 Nitto Denko Corp 保護テープの貼付方法およびその装置並びに保護テープの剥離方法
JP4137471B2 (ja) * 2002-03-04 2008-08-20 東京エレクトロン株式会社 ダイシング方法、集積回路チップの検査方法及び基板保持装置
JP2004079889A (ja) * 2002-08-21 2004-03-11 Disco Abrasive Syst Ltd 半導体ウェーハの製造方法
JP2005116610A (ja) * 2003-10-03 2005-04-28 Nitto Denko Corp 半導体ウエハの加工方法および半導体ウエハ加工用粘着シート
DE102004010956B9 (de) * 2004-03-03 2010-08-05 Infineon Technologies Ag Halbleiterbauteil mit einem dünnen Halbleiterchip und einem steifen Verdrahtungssubstrat sowie Verfahren zur Herstellung und Weiterverarbeitung von dünnen Halbleiterchips
JP4381860B2 (ja) 2004-03-24 2009-12-09 日東電工株式会社 補強半導体ウエハに固定された補強板の分離方法およびその装置
US7190058B2 (en) * 2004-04-01 2007-03-13 Chippac, Inc. Spacer die structure and method for attaching
JP2005302982A (ja) * 2004-04-12 2005-10-27 Nitto Denko Corp 半導体チップの製造方法
JP2005340655A (ja) * 2004-05-28 2005-12-08 Shinko Electric Ind Co Ltd 半導体装置の製造方法および半導体基板の支持構造体
JP2007095780A (ja) * 2005-09-27 2007-04-12 Oki Electric Ind Co Ltd 半導体装置製造用治具と半導体装置製造方法
GB0602410D0 (en) * 2006-02-07 2006-03-15 Filtronic Compound Semiconduct A method of bonding a semiconductor wafer to a support substrate
DE102006009394B4 (de) 2006-03-01 2025-07-31 Nissan Chemical Industries, Ltd. Mehrlagenschichtsystem mit einer Schicht als Trennschicht zum Trägern von dünnen Wafern bei der Halbleiterherstellung, Verwendung des Schichtsystems beim und Verfahren zum Abdünnen eines Wafers
DE102006048800B4 (de) 2006-10-16 2018-12-13 Nissan Chemical Industries, Ltd. Mehrlagenschichtsystem mit hartem Träger zum Trägern von dünnen Wafern bei der Halbleiterherstellung
DE102006048799B4 (de) 2006-10-16 2018-09-20 Nissan Chemical Industries, Ltd. Verfahren und Einrichtung zum Ablösen eines dünnen Wafers oder bereits vereinzelter Bauelemente eines dünnen Wafers von einem Träger
DE102006009353B4 (de) 2006-03-01 2025-03-27 Nissan Chemical Industries, Ltd. Mehrlagenschichtsystem zum Trägern von dünnen Wafern bei der Halbleiterherstellung mit der Eigenschaft zum Haltern mittels elektrostatischer Aufladung
JP5027460B2 (ja) * 2006-07-28 2012-09-19 東京応化工業株式会社 ウエハの接着方法、薄板化方法、及び剥離方法
JP5190222B2 (ja) * 2007-06-01 2013-04-24 日東電工株式会社 両面発泡粘着シートおよび液晶表示装置
JP2010056562A (ja) * 2009-11-26 2010-03-11 Nitto Denko Corp 半導体チップの製造方法
JP5348075B2 (ja) * 2010-06-02 2013-11-20 ソニー株式会社 半導体発光素子の製造方法、半導体素子の製造方法および素子の製造方法
GB2481187B (en) 2010-06-04 2014-10-29 Plastic Logic Ltd Processing substrates
JP5591859B2 (ja) * 2012-03-23 2014-09-17 株式会社東芝 基板の分離方法及び分離装置
JP2015217461A (ja) * 2014-05-16 2015-12-07 株式会社ディスコ ウェーハの加工方法
CN106206382A (zh) * 2016-08-30 2016-12-07 浙江中纳晶微电子科技有限公司 薄片状工件临时键合的加工方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5956471A (ja) 1982-09-24 1984-03-31 Nitto Electric Ind Co Ltd 両面接着テ−プの製造方法
JPH05291397A (ja) * 1992-04-07 1993-11-05 Toshiba Corp コレットおよび半導体装置の製造方法
US5476566A (en) * 1992-09-02 1995-12-19 Motorola, Inc. Method for thinning a semiconductor wafer
JPH0774131A (ja) * 1993-09-02 1995-03-17 Matsushita Electric Ind Co Ltd ダイシング装置及び半導体チップの加工方法
US6342434B1 (en) * 1995-12-04 2002-01-29 Hitachi, Ltd. Methods of processing semiconductor wafer, and producing IC card, and carrier
JPH10284449A (ja) * 1997-04-11 1998-10-23 Disco Abrasive Syst Ltd ウェーハの裏面研磨・ダイシング方法及びシステム
DK0999853T3 (da) 1997-06-13 2003-04-22 Genentech Inc Stabiliseret antostofformulering
US6162703A (en) * 1998-02-23 2000-12-19 Micron Technology, Inc. Packaging die preparation
JP2000038556A (ja) * 1998-07-22 2000-02-08 Nitto Denko Corp 半導体ウエハ保持保護用ホットメルトシート及びその貼り付け方法
JP3784202B2 (ja) * 1998-08-26 2006-06-07 リンテック株式会社 両面粘着シートおよびその使用方法
DE19850873A1 (de) 1998-11-05 2000-05-11 Philips Corp Intellectual Pty Verfahren zum Bearbeiten eines Erzeugnisses der Halbleitertechnik
DE19962763C2 (de) 1999-07-01 2001-07-26 Fraunhofer Ges Forschung Verfahren zum Vereinzeln eines Wafers

Also Published As

Publication number Publication date
EP1316111A2 (de) 2003-06-04
WO2002019393A2 (en) 2002-03-07
US6803293B2 (en) 2004-10-12
US20040038469A1 (en) 2004-02-26
PT1316111E (pt) 2011-03-23
WO2002019393A3 (en) 2002-06-06
KR20030029152A (ko) 2003-04-11
DE60143987D1 (de) 2011-03-17
KR100811958B1 (ko) 2008-03-10
EP1316111B1 (de) 2011-02-02
JP2002075937A (ja) 2002-03-15
TW518721B (en) 2003-01-21

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