ATE504037T1 - Vorrichtung und verfahren für konfigurierbare verarbeitung - Google Patents

Vorrichtung und verfahren für konfigurierbare verarbeitung

Info

Publication number
ATE504037T1
ATE504037T1 AT06727002T AT06727002T ATE504037T1 AT E504037 T1 ATE504037 T1 AT E504037T1 AT 06727002 T AT06727002 T AT 06727002T AT 06727002 T AT06727002 T AT 06727002T AT E504037 T1 ATE504037 T1 AT E504037T1
Authority
AT
Austria
Prior art keywords
instruction
configurable
operator
unit comprises
configuration information
Prior art date
Application number
AT06727002T
Other languages
English (en)
Inventor
Simon Knowles
Original Assignee
Icera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Icera Inc filed Critical Icera Inc
Application granted granted Critical
Publication of ATE504037T1 publication Critical patent/ATE504037T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Logic Circuits (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
  • Electrotherapy Devices (AREA)
  • Hardware Redundancy (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
AT06727002T 2005-05-05 2006-05-04 Vorrichtung und verfahren für konfigurierbare verarbeitung ATE504037T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/122,385 US8966223B2 (en) 2005-05-05 2005-05-05 Apparatus and method for configurable processing
PCT/GB2006/001629 WO2006117562A1 (en) 2005-05-05 2006-05-04 Apparatus and method for configurable processing

Publications (1)

Publication Number Publication Date
ATE504037T1 true ATE504037T1 (de) 2011-04-15

Family

ID=36659717

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06727002T ATE504037T1 (de) 2005-05-05 2006-05-04 Vorrichtung und verfahren für konfigurierbare verarbeitung

Country Status (10)

Country Link
US (2) US8966223B2 (de)
EP (1) EP1877896B1 (de)
JP (1) JP4806009B2 (de)
KR (1) KR20080015836A (de)
CN (1) CN101218560B (de)
AT (1) ATE504037T1 (de)
CA (1) CA2606558A1 (de)
DE (1) DE602006021000D1 (de)
TW (1) TWI439928B (de)
WO (1) WO2006117562A1 (de)

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GB0721427D0 (en) 2007-10-31 2007-12-12 Icera Inc Processing signals in a wireless newtwork
GB2454914B (en) 2007-11-22 2012-07-25 Icera Inc Clock control
GB2459733B (en) 2008-04-30 2012-12-19 Icera Inc Clock configuration
GB2459939B (en) 2008-05-16 2012-02-15 Icera Inc Fetching descriptors in a multiple context DMA engine
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US8078833B2 (en) * 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
CN101630305B (zh) * 2008-07-16 2011-05-11 中国人民解放军信息工程大学 高效能计算机中可重构部件的柔性管理方法
GB0818918D0 (en) 2008-10-15 2008-11-19 Icera Inc Boot algorithm
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GB2466982B (en) 2009-01-16 2013-07-17 Nvidia Technology Uk Ltd DMA Engine
GB2467760B (en) 2009-02-12 2013-05-22 Icera Inc Method for generating transmitter power amplifier ramp profiles from a single reference ramp pattern
GB0910850D0 (en) 2009-06-23 2009-08-05 Icera Inc Processing signals in a wireless network
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CN102043755B (zh) * 2009-10-22 2012-12-05 财团法人工业技术研究院 可重组态处理装置及其系统
GB2483225B (en) 2010-08-27 2018-07-11 Nvidia Tech Uk Limited Improved processor architecture
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US10255228B2 (en) * 2011-12-06 2019-04-09 Nvidia Corporation System and method for performing shaped memory access operations
US9558006B2 (en) * 2012-12-20 2017-01-31 Intel Corporation Continuous automatic tuning of code regions
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10019260B2 (en) * 2013-09-20 2018-07-10 Via Alliance Semiconductor Co., Ltd Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match
CN106796504B (zh) * 2014-07-30 2019-08-13 线性代数技术有限公司 用于管理可变长度指令的方法和设备
EP3125109B1 (de) 2015-07-31 2019-02-20 ARM Limited Vektorlängenabfrageanweisung
US10860322B2 (en) * 2015-10-30 2020-12-08 Arm Limited Modifying behavior of a data processing unit using rewritable behavior mappings of instructions
US9977677B2 (en) * 2016-04-07 2018-05-22 International Business Machines Corporation Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
US9734126B1 (en) 2016-10-10 2017-08-15 International Business Machines Corporation Post-silicon configurable instruction behavior based on input operands
US10963265B2 (en) * 2017-04-21 2021-03-30 Micron Technology, Inc. Apparatus and method to switch configurable logic units
US10409615B2 (en) * 2017-06-19 2019-09-10 The Regents Of The University Of Michigan Configurable arithmetic unit
JP7032647B2 (ja) * 2018-04-17 2022-03-09 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication
US11500644B2 (en) * 2020-05-15 2022-11-15 Alibaba Group Holding Limited Custom instruction implemented finite state machine engines for extensible processors
CN112783614A (zh) * 2021-01-20 2021-05-11 北京百度网讯科技有限公司 对象处理方法、装置、设备、存储介质以及程序产品
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Also Published As

Publication number Publication date
TW200707280A (en) 2007-02-16
JP2008541216A (ja) 2008-11-20
WO2006117562A1 (en) 2006-11-09
DE602006021000D1 (de) 2011-05-12
JP4806009B2 (ja) 2011-11-02
US8671268B2 (en) 2014-03-11
CN101218560A (zh) 2008-07-09
US8966223B2 (en) 2015-02-24
KR20080015836A (ko) 2008-02-20
CN101218560B (zh) 2012-06-06
EP1877896B1 (de) 2011-03-30
TWI439928B (zh) 2014-06-01
CA2606558A1 (en) 2006-11-09
EP1877896A1 (de) 2008-01-16
US20110161640A1 (en) 2011-06-30
US20060253689A1 (en) 2006-11-09

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