ATE504114T1 - Schaltungsanordnung, insbesondere phasenregelkreis, sowie entsprechendes verfahren - Google Patents

Schaltungsanordnung, insbesondere phasenregelkreis, sowie entsprechendes verfahren

Info

Publication number
ATE504114T1
ATE504114T1 AT06727924T AT06727924T ATE504114T1 AT E504114 T1 ATE504114 T1 AT E504114T1 AT 06727924 T AT06727924 T AT 06727924T AT 06727924 T AT06727924 T AT 06727924T AT E504114 T1 ATE504114 T1 AT E504114T1
Authority
AT
Austria
Prior art keywords
unit
digital
phase
oscillator
output signal
Prior art date
Application number
AT06727924T
Other languages
English (en)
Inventor
Ulrich Moehlmann
Timo Giesselmann
Edwin Schapendonk
Frank Brand
Den Broeke Leendert Van
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE504114T1 publication Critical patent/ATE504114T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)
  • Stereo-Broadcasting Methods (AREA)
AT06727924T 2005-04-18 2006-04-13 Schaltungsanordnung, insbesondere phasenregelkreis, sowie entsprechendes verfahren ATE504114T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05103069 2005-04-18
PCT/IB2006/051156 WO2006111899A2 (en) 2005-04-18 2006-04-13 Circuit arrangement, in particular phase-locked loop, as well as corresponding method

Publications (1)

Publication Number Publication Date
ATE504114T1 true ATE504114T1 (de) 2011-04-15

Family

ID=37442064

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06727924T ATE504114T1 (de) 2005-04-18 2006-04-13 Schaltungsanordnung, insbesondere phasenregelkreis, sowie entsprechendes verfahren

Country Status (7)

Country Link
US (1) US7557623B2 (de)
EP (1) EP1875610B1 (de)
JP (1) JP2008537425A (de)
CN (1) CN101160722A (de)
AT (1) ATE504114T1 (de)
DE (1) DE602006020997D1 (de)
WO (1) WO2006111899A2 (de)

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US7675332B1 (en) * 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
US7974807B2 (en) * 2008-09-18 2011-07-05 Qualcomm Incorporated Adaptive calibration for digital phase-locked loops
TWI364169B (en) * 2008-12-09 2012-05-11 Sunplus Technology Co Ltd All digital phase locked loop circuit
KR101056015B1 (ko) 2009-01-08 2011-08-10 한국과학기술원 높은 차수의 노이즈 쉐이핑이 가능한 시간-디지털 변환기 및 시간-디지털 변환 방법
US8638138B2 (en) * 2009-09-14 2014-01-28 Achronix Semiconductor Corporation Hierarchical global clock tree
US8339165B2 (en) 2009-12-07 2012-12-25 Qualcomm Incorporated Configurable digital-analog phase locked loop
US8446191B2 (en) 2009-12-07 2013-05-21 Qualcomm Incorporated Phase locked loop with digital compensation for analog integration
KR101729136B1 (ko) 2010-08-19 2017-04-24 삼성전자주식회사 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법
GB2483898B (en) * 2010-09-24 2015-07-22 Cambridge Silicon Radio Ltd Injection-locked oscillator
US8242824B1 (en) * 2011-01-28 2012-08-14 Faraday Technology Corp. Signal delay apparatus for providing exact delay amount, memory apparatus utilizing the signal delay apparatus, and signal delay method
US8855215B2 (en) * 2011-05-09 2014-10-07 The Royal Institution For The Advancement Of Learning/Mcgill University Phase/frequency synthesis using periodic sigma-delta modulated bit-stream techniques
CN103633998B (zh) * 2012-08-28 2017-02-15 复旦大学 一种用于全数字锁相环的低功耗鉴相器
US9240914B2 (en) * 2013-01-15 2016-01-19 Samsung Electronics Co., Ltd. Communication system with frequency synthesis mechanism and method of operation thereof
US9331722B2 (en) * 2013-12-26 2016-05-03 Intel IP Corporation Feedback calibration of digital to time converter
US9395698B2 (en) * 2014-10-14 2016-07-19 Intel Corporation Bang-bang time to digital converter systems and methods
US10163385B2 (en) 2015-04-10 2018-12-25 Apple Inc. Display driver circuitry with selectively enabled clock distribution
US9740175B2 (en) * 2016-01-18 2017-08-22 Marvell World Trade Ltd. All-digital phase locked loop (ADPLL) including a digital-to-time converter (DTC) and a sampling time-to-digital converter (TDC)
CN106054856B (zh) * 2016-05-26 2019-04-12 中广核研究院有限公司北京分公司 基于核电站比例积分控制器的噪声分析方法及装置
US10250264B2 (en) * 2016-06-21 2019-04-02 Marvell World Trade Ltd. Multiplying delay-locked loop using sampling time-to-digital converter
US10340926B2 (en) * 2016-10-03 2019-07-02 Analog Devices Global Fast settling sawtooth ramp generation in a phase-locked loop
CN106681127B (zh) * 2016-12-22 2019-02-01 建荣半导体（深圳）有限公司 移位寄存器电路、相位差计算方法及时间数字转换器
CN106772185B (zh) * 2017-01-11 2020-03-10 深圳市鼎阳科技股份有限公司 一种用于示波器的信号间隔或周期检测方法和装置
US10320401B2 (en) * 2017-10-13 2019-06-11 Xilinx, Inc. Dual-path digital-to-time converter
US10707879B2 (en) * 2018-04-13 2020-07-07 KaiKuTek Inc. Frequency-modulated continuous-wave radar system and frequency tracking method for calibrating frequency gains of a radio frequency signal to approach wideband flatness frequency responses
CN111030679B (zh) * 2018-10-09 2023-03-07 华邦电子股份有限公司 延迟锁相回路电路及其单位粗延迟选择方法
CN109150168B (zh) * 2018-10-11 2023-08-29 南华大学 流水线电路结构的全数字锁相环及锁相控制方法
US10608647B1 (en) * 2018-12-14 2020-03-31 Silicon Laboratories Inc. Delay adjustment using frequency estimation
EP3672070A1 (de) * 2018-12-19 2020-06-24 Nxp B.V. Kommunikationsvorrichtung und verfahren zum betrieb einer kommunikationsvorrichtung
US10727845B1 (en) * 2019-06-25 2020-07-28 Silicon Laboratories Inc. Use of a virtual clock in a PLL to maintain a closed loop system
US10908635B1 (en) 2019-12-24 2021-02-02 Silicon Laboratories Inc. Detection and management of frequency errors in a reference input clock signal
CN112260684B (zh) * 2020-12-21 2021-04-02 上海国微思尔芯技术股份有限公司 一种用于原型验证系统的时钟对齐系统及方法

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US5832048A (en) 1993-12-30 1998-11-03 International Business Machines Corporation Digital phase-lock loop control system
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US8385476B2 (en) * 2001-04-25 2013-02-26 Texas Instruments Incorporated Digital phase locked loop
US7124153B2 (en) 2002-03-18 2006-10-17 Genesis Microchip Inc. Frequency converter and methods of use thereof
US7061276B2 (en) * 2004-04-02 2006-06-13 Teradyne, Inc. Digital phase detector

Also Published As

Publication number Publication date
US20080204092A1 (en) 2008-08-28
EP1875610B1 (de) 2011-03-30
CN101160722A (zh) 2008-04-09
WO2006111899A2 (en) 2006-10-26
EP1875610A2 (de) 2008-01-09
JP2008537425A (ja) 2008-09-11
DE602006020997D1 (de) 2011-05-12
WO2006111899A3 (en) 2007-03-15
US7557623B2 (en) 2009-07-07

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