ATE504879T1 - Elektronische anordnung mit cpu und interrupt- relaisstufe - Google Patents

Elektronische anordnung mit cpu und interrupt- relaisstufe

Info

Publication number
ATE504879T1
ATE504879T1 AT08774746T AT08774746T ATE504879T1 AT E504879 T1 ATE504879 T1 AT E504879T1 AT 08774746 T AT08774746 T AT 08774746T AT 08774746 T AT08774746 T AT 08774746T AT E504879 T1 ATE504879 T1 AT E504879T1
Authority
AT
Austria
Prior art keywords
interrupt
processing unit
central processing
cpu
electronic arrangement
Prior art date
Application number
AT08774746T
Other languages
English (en)
Inventor
Joerg Schreiner
Original Assignee
Texas Instruments Deutschland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Deutschland filed Critical Texas Instruments Deutschland
Application granted granted Critical
Publication of ATE504879T1 publication Critical patent/ATE504879T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
AT08774746T 2007-07-06 2008-07-03 Elektronische anordnung mit cpu und interrupt- relaisstufe ATE504879T1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102007031529A DE102007031529B4 (de) 2007-07-06 2007-07-06 Elektronisches Gerät und Verfahren zum Umschalten einer CPU von einer ersten in eine zweite Betriebsart
US1672807P 2007-12-26 2007-12-26
US12/146,634 US20090070566A1 (en) 2007-07-06 2008-06-26 Electronic Device With CPU and Interrupt Relay Stage
PCT/EP2008/058634 WO2009007309A1 (en) 2007-07-06 2008-07-03 Electronic device with cpu and interrupt relay stage

Publications (1)

Publication Number Publication Date
ATE504879T1 true ATE504879T1 (de) 2011-04-15

Family

ID=40092500

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08774746T ATE504879T1 (de) 2007-07-06 2008-07-03 Elektronische anordnung mit cpu und interrupt- relaisstufe

Country Status (5)

Country Link
US (1) US20090070566A1 (de)
EP (1) EP2186010B1 (de)
AT (1) ATE504879T1 (de)
DE (2) DE102007031529B4 (de)
WO (1) WO2009007309A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8812761B2 (en) * 2011-10-28 2014-08-19 Apple Inc. System and method for adjusting power usage to reduce interrupt latency
US20160187958A1 (en) * 2014-12-24 2016-06-30 Intel Corporation Techniques for managing power and performance for a networking device
US10845195B2 (en) 2015-07-01 2020-11-24 Solitonreach, Inc. System and method for motion based alignment of body parts
US10698501B2 (en) * 2015-07-01 2020-06-30 Solitonreach, Inc. Systems and methods for three dimensional control of mobile applications
US10462059B2 (en) 2016-10-19 2019-10-29 Intel Corporation Hash table entries insertion method and apparatus using virtual buckets
JP6402798B2 (ja) * 2017-04-05 2018-10-10 株式会社デンソー 車両パワーウインドウ装置用の制御装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5551044A (en) * 1994-12-01 1996-08-27 Intel Corporation Method and apparatus for interrupt/SMI# ordering
US6807595B2 (en) * 2001-05-10 2004-10-19 Qualcomm Incorporated Mobile communication device having a prioritized interrupt controller
JP4726337B2 (ja) * 2001-06-27 2011-07-20 ルネサスエレクトロニクス株式会社 ワンチップマイクロコンピュータ
US7724169B2 (en) * 2008-02-12 2010-05-25 National Semiconductor Corporation Semiconductor chip with a number of A/D converters that include a group of redundant A/D converters

Also Published As

Publication number Publication date
WO2009007309A1 (en) 2009-01-15
EP2186010A1 (de) 2010-05-19
DE602008006096D1 (de) 2011-05-19
DE102007031529A1 (de) 2009-01-08
DE102007031529B4 (de) 2010-07-22
US20090070566A1 (en) 2009-03-12
EP2186010B1 (de) 2011-04-06

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Legal Events

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