ATE504921T1 - S-ram-speicher mit magnetischer vergleichszelle - Google Patents

S-ram-speicher mit magnetischer vergleichszelle

Info

Publication number
ATE504921T1
ATE504921T1 AT08164774T AT08164774T ATE504921T1 AT E504921 T1 ATE504921 T1 AT E504921T1 AT 08164774 T AT08164774 T AT 08164774T AT 08164774 T AT08164774 T AT 08164774T AT E504921 T1 ATE504921 T1 AT E504921T1
Authority
AT
Austria
Prior art keywords
transistor
another
ram memory
comparison cell
cell
Prior art date
Application number
AT08164774T
Other languages
English (en)
Inventor
Olivier Thomas
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE504921T1 publication Critical patent/ATE504921T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT08164774T 2007-09-24 2008-09-22 S-ram-speicher mit magnetischer vergleichszelle ATE504921T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0757792A FR2921508A1 (fr) 2007-09-24 2007-09-24 Memoire sram a cellule de reference de polarisation

Publications (1)

Publication Number Publication Date
ATE504921T1 true ATE504921T1 (de) 2011-04-15

Family

ID=38920572

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08164774T ATE504921T1 (de) 2007-09-24 2008-09-22 S-ram-speicher mit magnetischer vergleichszelle

Country Status (5)

Country Link
US (1) US7787286B2 (de)
EP (1) EP2040264B1 (de)
AT (1) ATE504921T1 (de)
DE (1) DE602008005977D1 (de)
FR (1) FR2921508A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2910999B1 (fr) * 2006-12-28 2009-04-03 Commissariat Energie Atomique Cellule memoire dotee de transistors double-grille, a grilles independantes et asymetriques
JP5278971B2 (ja) * 2010-03-30 2013-09-04 独立行政法人産業技術総合研究所 Ｓｒａｍ装置
US8432724B2 (en) 2010-04-02 2013-04-30 Altera Corporation Memory elements with soft error upset immunity
US9865330B2 (en) * 2010-11-04 2018-01-09 Qualcomm Incorporated Stable SRAM bitcell design utilizing independent gate FinFET
US8964451B2 (en) * 2011-03-09 2015-02-24 Douglas P. Sheppard Memory cell system and method
US9001571B1 (en) * 2014-01-20 2015-04-07 National Tsing Hua University 6T static random access memory cell, array and memory thereof
US12336190B2 (en) * 2021-07-21 2025-06-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and fabrication thereof
CN113674773B (zh) * 2021-08-17 2025-11-25 晟合微电子(肇庆)有限公司 显示器及半导体存储器件

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100200765B1 (ko) 1996-12-04 1999-06-15 윤종용 레이아웃 면적이 감소되는 sram 셀
US5793671A (en) 1997-01-21 1998-08-11 Advanced Micro Devices, Inc. Static random access memory cell utilizing enhancement mode N-channel transistors as load elements
JPH118390A (ja) 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6937538B2 (en) * 2000-02-02 2005-08-30 Broadcom Corporation Asynchronously resettable decoder for a semiconductor memory
US6442060B1 (en) 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
US6731533B2 (en) 2000-10-31 2004-05-04 Texas Instruments Incorporated Loadless 4T SRAM cell with PMOS drivers
US6529400B1 (en) 2000-12-15 2003-03-04 Lsi Logic Corporation Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells
FR2853445B1 (fr) 2003-04-02 2005-10-14 Amara Amara Cellule memoire statique a acces aleatoire(sram), et unite memoire a ultra basse consommation realisee a partir de telles cellules
JP2005142289A (ja) 2003-11-05 2005-06-02 Toshiba Corp 半導体記憶装置
US7224029B2 (en) 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
US20060187700A1 (en) 2005-02-08 2006-08-24 Iota Technology, Inc. Single event effect (SEE) tolerant circuit design strategy for SOI type technology
FR2884648B1 (fr) 2005-04-13 2007-09-07 Commissariat Energie Atomique Structure et procede de realisation d'un dispositif microelectronique dote d'un ou plusieurs fils quantiques aptes a former un canal ou plusieurs canaux de transistors
US7532501B2 (en) * 2005-06-02 2009-05-12 International Business Machines Corporation Semiconductor device including back-gated transistors and method of fabricating the device
JP5054919B2 (ja) 2005-12-20 2012-10-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP4855786B2 (ja) * 2006-01-25 2012-01-18 株式会社東芝 半導体装置
FR2898432B1 (fr) * 2006-03-10 2008-04-11 Commissariat Energie Atomique Cellules memoire en technologie cmos double-grille dotee de transistors a deux grilles independantes

Also Published As

Publication number Publication date
EP2040264A1 (de) 2009-03-25
FR2921508A1 (fr) 2009-03-27
US20090080237A1 (en) 2009-03-26
EP2040264B1 (de) 2011-04-06
US7787286B2 (en) 2010-08-31
DE602008005977D1 (de) 2011-05-19

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Legal Events

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