ATE523882T1 - Sram-speicherzelle auf basis von doppelgate- transistoren mit mittel zur erweiterung eines schreibbereichs - Google Patents

Sram-speicherzelle auf basis von doppelgate- transistoren mit mittel zur erweiterung eines schreibbereichs

Info

Publication number
ATE523882T1
ATE523882T1 AT09712534T AT09712534T ATE523882T1 AT E523882 T1 ATE523882 T1 AT E523882T1 AT 09712534 T AT09712534 T AT 09712534T AT 09712534 T AT09712534 T AT 09712534T AT E523882 T1 ATE523882 T1 AT E523882T1
Authority
AT
Austria
Prior art keywords
double
memory cell
expanding
cell based
gate transistors
Prior art date
Application number
AT09712534T
Other languages
English (en)
Inventor
Olivier Thomas
Bastien Giraud
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE523882T1 publication Critical patent/ATE523882T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
AT09712534T 2008-02-18 2009-02-16 Sram-speicherzelle auf basis von doppelgate- transistoren mit mittel zur erweiterung eines schreibbereichs ATE523882T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0851027A FR2927722A1 (fr) 2008-02-18 2008-02-18 Cellule memoire sram a transistor double grille dotee de moyens pour ameliorer la marge en ecriture
PCT/EP2009/051819 WO2009103687A1 (fr) 2008-02-18 2009-02-16 Cellule mémoire sram à transistors double grille dotee de moyens pour ameliorer la marge en ecriture

Publications (1)

Publication Number Publication Date
ATE523882T1 true ATE523882T1 (de) 2011-09-15

Family

ID=39462188

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09712534T ATE523882T1 (de) 2008-02-18 2009-02-16 Sram-speicherzelle auf basis von doppelgate- transistoren mit mittel zur erweiterung eines schreibbereichs

Country Status (6)

Country Link
US (1) US8320198B2 (de)
EP (1) EP2245632B1 (de)
JP (1) JP2011512609A (de)
AT (1) ATE523882T1 (de)
FR (1) FR2927722A1 (de)
WO (1) WO2009103687A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7440313B2 (en) * 2006-11-17 2008-10-21 Freescale Semiconductor, Inc. Two-port SRAM having improved write operation
US8879461B2 (en) 2008-12-01 2014-11-04 Qualcomm Incorporated Blank subframe uplink design
US8559213B2 (en) * 2009-08-13 2013-10-15 Southeast University Sub-threshold memory cell circuit with high density and high robustness
KR101481399B1 (ko) * 2009-12-18 2015-01-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
IT1397216B1 (it) * 2009-12-29 2013-01-04 St Microelectronics Srl Dispositivo di memoria sram
JP5278971B2 (ja) * 2010-03-30 2013-09-04 独立行政法人産業技術総合研究所 Ｓｒａｍ装置
US8305798B2 (en) * 2010-07-13 2012-11-06 Texas Instruments Incorporated Memory cell with equalization write assist in solid-state memory
US9865330B2 (en) * 2010-11-04 2018-01-09 Qualcomm Incorporated Stable SRAM bitcell design utilizing independent gate FinFET
JP5711612B2 (ja) 2011-05-24 2015-05-07 ルネサスエレクトロニクス株式会社 半導体装置
US9269409B2 (en) * 2011-10-18 2016-02-23 Intel Corporation Bit cell write-assistance
US9299395B2 (en) * 2012-03-26 2016-03-29 Intel Corporation Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks
US9230637B1 (en) 2014-09-09 2016-01-05 Globalfoundries Inc. SRAM circuit with increased write margin
JP2020202005A (ja) * 2020-07-30 2020-12-17 株式会社半導体エネルギー研究所 半導体装置

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JPS62217494A (ja) * 1986-03-18 1987-09-24 Fujitsu Ltd 半導体記憶装置
KR100200765B1 (ko) * 1996-12-04 1999-06-15 윤종용 레이아웃 면적이 감소되는 sram 셀
US5793671A (en) * 1997-01-21 1998-08-11 Advanced Micro Devices, Inc. Static random access memory cell utilizing enhancement mode N-channel transistors as load elements
US5991192A (en) 1997-12-08 1999-11-23 National Science Council Of Republic Of China Current-mode write-circuit of a static ram
JP2002042476A (ja) * 2000-07-25 2002-02-08 Mitsubishi Electric Corp スタティック型半導体記憶装置
US6529400B1 (en) * 2000-12-15 2003-03-04 Lsi Logic Corporation Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells
JP4850387B2 (ja) * 2002-12-09 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
US6839299B1 (en) * 2003-07-24 2005-01-04 International Business Machines Corporation Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells
JP4423392B2 (ja) * 2004-12-10 2010-03-03 独立行政法人産業技術総合研究所 二重絶縁ゲート電界トランジスタを用いたｍｏｓトランジスタ回路およびそれを用いたｃｍｏｓトランジスタ回路、ｓｒａｍセル回路、ｃｍｏｓ−ｓｒａｍセル回路、集積回路
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WO2007048232A1 (en) * 2005-10-26 2007-05-03 Manoj Sachdev Segmented column virtual ground scheme in a static random access memory (sram) circuit
JP5054919B2 (ja) * 2005-12-20 2012-10-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US20070183185A1 (en) * 2006-01-11 2007-08-09 The Regents Of The University Of California Finfet-based sram with feedback
JP4855786B2 (ja) * 2006-01-25 2012-01-18 株式会社東芝 半導体装置
JP5119489B2 (ja) * 2006-03-07 2013-01-16 公益財団法人新産業創造研究機構 半導体記憶装置
FR2898432B1 (fr) 2006-03-10 2008-04-11 Commissariat Energie Atomique Cellules memoire en technologie cmos double-grille dotee de transistors a deux grilles independantes
FR2911004B1 (fr) 2006-12-28 2009-05-15 Commissariat Energie Atomique Procede de realisation de transistors a double-grille asymetriques permettant la realisation de transistors a double-grille asymetriques et symetriques sur un meme substrat
FR2918794B1 (fr) 2007-07-09 2010-04-30 Commissariat Energie Atomique Cellule memoire sram non-volatile dotee de transistors a grille mobile et actionnement piezoelectrique.
FR2932003B1 (fr) 2008-06-02 2011-03-25 Commissariat Energie Atomique Cellule de memoire sram a transistor integres sur plusieurs niveaux et dont la tension de seuil vt est ajustable dynamiquement
US7782655B2 (en) * 2008-07-01 2010-08-24 Jeng-Jye Shau Ultra-low power hybrid sub-threshold circuits

Also Published As

Publication number Publication date
JP2011512609A (ja) 2011-04-21
WO2009103687A1 (fr) 2009-08-27
EP2245632B1 (de) 2011-09-07
US20100315889A1 (en) 2010-12-16
EP2245632A1 (de) 2010-11-03
FR2927722A1 (fr) 2009-08-21
US8320198B2 (en) 2012-11-27

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