ATE506694T1 - Verfahren zur herstellung eines gate- dielektrikums mit gebieten hoher und niedriger dielektrizitätskonstante - Google Patents

Verfahren zur herstellung eines gate- dielektrikums mit gebieten hoher und niedriger dielektrizitätskonstante

Info

Publication number
ATE506694T1
ATE506694T1 AT02368012T AT02368012T ATE506694T1 AT E506694 T1 ATE506694 T1 AT E506694T1 AT 02368012 T AT02368012 T AT 02368012T AT 02368012 T AT02368012 T AT 02368012T AT E506694 T1 ATE506694 T1 AT E506694T1
Authority
AT
Austria
Prior art keywords
dielectric layer
low
gate opening
producing
gate dielectric
Prior art date
Application number
AT02368012T
Other languages
English (en)
Inventor
Lap Chan
Elgin Quek
Ravi Sundaresan
Yang Pan
James Yong Meng Lee
Ying Keung Leung
Yelehanka Ramachandramurthy Pradeep
Jia Zhen Zheng
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Application granted granted Critical
Publication of ATE506694T1 publication Critical patent/ATE506694T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
AT02368012T 2001-01-26 2002-01-25 Verfahren zur herstellung eines gate- dielektrikums mit gebieten hoher und niedriger dielektrizitätskonstante ATE506694T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/769,810 US6406945B1 (en) 2001-01-26 2001-01-26 Method for forming a transistor gate dielectric with high-K and low-K regions

Publications (1)

Publication Number Publication Date
ATE506694T1 true ATE506694T1 (de) 2011-05-15

Family

ID=25086565

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02368012T ATE506694T1 (de) 2001-01-26 2002-01-25 Verfahren zur herstellung eines gate- dielektrikums mit gebieten hoher und niedriger dielektrizitätskonstante

Country Status (7)

Country Link
US (1) US6406945B1 (de)
EP (1) EP1227514B1 (de)
JP (1) JP2002289851A (de)
AT (1) ATE506694T1 (de)
DE (1) DE60239771D1 (de)
SG (1) SG99379A1 (de)
TW (1) TW488018B (de)

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US20020179982A1 (en) * 2001-05-29 2002-12-05 United Microelectronics Corp. MOS field effect transistor structure and method of manufacture
US6762463B2 (en) * 2001-06-09 2004-07-13 Advanced Micro Devices, Inc. MOSFET with SiGe source/drain regions and epitaxial gate dielectric
US6713357B1 (en) * 2001-12-20 2004-03-30 Advanced Micro Devices, Inc. Method to reduce parasitic capacitance of MOS transistors
US6617209B1 (en) * 2002-02-22 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7187031B2 (en) * 2002-05-31 2007-03-06 Sharp Kabushiki Kaisha Semiconductor device having a low dielectric constant film and manufacturing method thereof
US6806149B2 (en) * 2002-09-26 2004-10-19 Texas Instruments Incorporated Sidewall processes using alkylsilane precursors for MOS transistor fabrication
US6746900B1 (en) * 2003-02-19 2004-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor device having high-K gate dielectric material
KR100486654B1 (ko) 2003-08-07 2005-05-03 동부아남반도체 주식회사 반도체의 삼중 게이트 산화막 형성방법
US20050259467A1 (en) * 2004-05-18 2005-11-24 Micron Technology, Inc. Split gate flash memory cell with ballistic injection
US7196935B2 (en) * 2004-05-18 2007-03-27 Micron Technolnology, Inc. Ballistic injection NROM flash memory
US20060043462A1 (en) * 2004-08-27 2006-03-02 Micron Technology, Inc. Stepped gate configuration for non-volatile memory
DE102004044667A1 (de) * 2004-09-15 2006-03-16 Infineon Technologies Ag Halbleiterbauelement sowie zugehöriges Herstellungsverfahren
US20060157750A1 (en) * 2005-01-20 2006-07-20 Samsung Electronics Co., Ltd. Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
KR100647314B1 (ko) * 2005-01-31 2006-11-23 삼성전자주식회사 나노 임프린트 리소그래피용 정렬시스템 및 이를 채용한임프린트 리소그래피 방법
US7365378B2 (en) * 2005-03-31 2008-04-29 International Business Machines Corporation MOSFET structure with ultra-low K spacer
KR100596802B1 (ko) * 2005-05-27 2006-07-04 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7349196B2 (en) * 2005-06-17 2008-03-25 Industrial Technology Research Institute Composite distributed dielectric structure
TWI312177B (en) 2006-03-15 2009-07-11 Promos Technologies Inc Recessed gate structure and method for preparing the same
TW200735222A (en) 2006-03-15 2007-09-16 Promos Technologies Inc Multi-steps gate structure and method for preparing the same
JP2009070849A (ja) * 2007-09-10 2009-04-02 Rohm Co Ltd 半導体装置
US7964467B2 (en) * 2008-03-26 2011-06-21 International Business Machines Corporation Method, structure and design structure for customizing history effects of soi circuits
US8420460B2 (en) 2008-03-26 2013-04-16 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
US8410554B2 (en) * 2008-03-26 2013-04-02 International Business Machines Corporation Method, structure and design structure for customizing history effects of SOI circuits
JP2012060063A (ja) 2010-09-13 2012-03-22 Toshiba Corp 半導体装置及びその製造方法
JP2012099517A (ja) 2010-10-29 2012-05-24 Sony Corp 半導体装置及び半導体装置の製造方法
KR101737490B1 (ko) * 2010-11-11 2017-05-18 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN102479746B (zh) * 2010-11-29 2013-11-20 中芯国际集成电路制造(上海)有限公司 减少金属栅电极和接触孔之间寄生电容的方法
US8642424B2 (en) 2011-07-12 2014-02-04 International Business Machines Corporation Replacement metal gate structure and methods of manufacture
US8941177B2 (en) 2012-06-27 2015-01-27 International Business Machines Corporation Semiconductor devices having different gate oxide thicknesses
KR102167625B1 (ko) * 2013-10-24 2020-10-19 삼성전자주식회사 반도체 장치 및 그 제조 방법
EP3179514B1 (de) 2015-12-11 2024-01-24 IMEC vzw Transistorvorrichtung mit einer reduzierten injektionswirkung von heissen ladungsträgern
KR102608084B1 (ko) * 2017-08-04 2023-11-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
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Also Published As

Publication number Publication date
TW488018B (en) 2002-05-21
SG99379A1 (en) 2003-10-27
DE60239771D1 (de) 2011-06-01
EP1227514A2 (de) 2002-07-31
EP1227514B1 (de) 2011-04-20
EP1227514A3 (de) 2003-12-03
US6406945B1 (en) 2002-06-18
JP2002289851A (ja) 2002-10-04

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