ATE508459T1 - System und verfahren zur verringerung des stromverbrauchs während erweiterter auffrischperioden von dynamischen direktzugriffsspeicherbausteinen - Google Patents
System und verfahren zur verringerung des stromverbrauchs während erweiterter auffrischperioden von dynamischen direktzugriffsspeicherbausteinenInfo
- Publication number
- ATE508459T1 ATE508459T1 AT05852054T AT05852054T ATE508459T1 AT E508459 T1 ATE508459 T1 AT E508459T1 AT 05852054 T AT05852054 T AT 05852054T AT 05852054 T AT05852054 T AT 05852054T AT E508459 T1 ATE508459 T1 AT E508459T1
- Authority
- AT
- Austria
- Prior art keywords
- voltage
- refresh mode
- power consumption
- random access
- dynamic random
- Prior art date
Links
- 230000003068 static effect Effects 0.000 abstract 3
- 239000003990 capacitor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4068—Voltage or leakage in refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/003,547 US7082073B2 (en) | 2004-12-03 | 2004-12-03 | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
| PCT/US2005/042420 WO2006060249A1 (en) | 2004-12-03 | 2005-11-22 | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE508459T1 true ATE508459T1 (de) | 2011-05-15 |
Family
ID=36565359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05852054T ATE508459T1 (de) | 2004-12-03 | 2005-11-22 | System und verfahren zur verringerung des stromverbrauchs während erweiterter auffrischperioden von dynamischen direktzugriffsspeicherbausteinen |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US7082073B2 (de) |
| EP (1) | EP1828716B1 (de) |
| JP (1) | JP4979589B2 (de) |
| KR (1) | KR100887527B1 (de) |
| CN (1) | CN101069062B (de) |
| AT (1) | ATE508459T1 (de) |
| DE (1) | DE602005027898D1 (de) |
| WO (1) | WO2006060249A1 (de) |
Families Citing this family (61)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6922367B2 (en) * | 2003-07-09 | 2005-07-26 | Micron Technology, Inc. | Data strobe synchronization circuit and method for double data rate, multi-bit writes |
| US7082073B2 (en) * | 2004-12-03 | 2006-07-25 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
| US7177222B2 (en) * | 2005-03-04 | 2007-02-13 | Seagate Technology Llc | Reducing power consumption in a data storage system |
| JP4879172B2 (ja) * | 2005-06-01 | 2012-02-22 | パナソニック株式会社 | 半導体記憶装置、及びそれを搭載した半導体集積回路 |
| US7580312B2 (en) | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
| US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
| US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
| US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
| US7392338B2 (en) | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
| GB2441726B (en) | 2005-06-24 | 2010-08-11 | Metaram Inc | An integrated memory core and memory interface circuit |
| US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
| US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
| US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
| US7386656B2 (en) | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
| US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
| US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
| US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
| US7472220B2 (en) | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
| US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
| US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
| US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
| US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
| US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
| US7590796B2 (en) | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
| US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
| US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
| US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
| US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
| US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
| US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
| US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
| US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
| US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
| US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
| JP5242397B2 (ja) | 2005-09-02 | 2013-07-24 | メタラム インコーポレイテッド | Ｄｒａｍをスタックする方法及び装置 |
| US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
| KR100810060B1 (ko) * | 2006-04-14 | 2008-03-05 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 그의 구동방법 |
| KR100780624B1 (ko) * | 2006-06-29 | 2007-11-29 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 구동방법 |
| US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
| US8004920B2 (en) | 2007-05-29 | 2011-08-23 | Micron Technology, Inc. | Power saving memory apparatus, systems, and methods |
| US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
| US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
| KR101596228B1 (ko) * | 2008-10-02 | 2016-02-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| US7990795B2 (en) | 2009-02-19 | 2011-08-02 | Freescale Semiconductor, Inc. | Dynamic random access memory (DRAM) refresh |
| WO2010144624A1 (en) | 2009-06-09 | 2010-12-16 | Google Inc. | Programming of dimm termination resistance values |
| JP2011146104A (ja) | 2010-01-15 | 2011-07-28 | Elpida Memory Inc | 半導体装置及び半導体装置を含む情報処理システム |
| TWI447741B (zh) * | 2010-07-29 | 2014-08-01 | Winbond Electronics Corp | 動態隨機存取記憶體單元及其資料更新方法 |
| CN103035281B (zh) * | 2011-09-29 | 2016-01-13 | 复旦大学 | 一种基于单元漏电检测的温度控制自刷新方法 |
| US8824230B2 (en) * | 2011-09-30 | 2014-09-02 | Qualcomm Incorporated | Method and apparatus of reducing leakage power in multiple port SRAM memory cell |
| KR101932663B1 (ko) | 2012-07-12 | 2018-12-26 | 삼성전자 주식회사 | 리프레쉬 주기 정보를 저장하는 반도체 메모리 장치 및 그 동작방법 |
| US9076548B1 (en) | 2012-11-22 | 2015-07-07 | Samsung Electronics Co., Ltd. | Semiconductor memory device including refresh control circuit and method of refreshing the same |
| US9905199B2 (en) * | 2014-09-17 | 2018-02-27 | Mediatek Inc. | Processor for use in dynamic refresh rate switching and related electronic device and method |
| TWI653527B (zh) * | 2014-12-27 | 2019-03-11 | 美商英特爾公司 | 當計算元件運作時致能系統低電力狀態之技術 |
| JP6633566B2 (ja) * | 2017-03-31 | 2020-01-22 | 株式会社メガチップス | 表示制御装置及び表示制御方法 |
| US10572183B2 (en) * | 2017-10-18 | 2020-02-25 | Advanced Micro Devices, Inc. | Power efficient retraining of memory accesses |
| US10783953B2 (en) * | 2017-12-04 | 2020-09-22 | Advanced Micro Devices, Inc. | Memory with expandable row width |
| US10923171B2 (en) | 2018-10-17 | 2021-02-16 | Micron Technology, Inc. | Semiconductor device performing refresh operation in deep sleep mode |
| US11348635B2 (en) * | 2020-03-30 | 2022-05-31 | Micron Technology, Inc. | Memory cell biasing techniques during a read operation |
| US11929130B2 (en) | 2020-09-30 | 2024-03-12 | Changxin Memory Technologies, Inc. | Method and device for testing sr cycle as well as method and device for testing ar number |
| CN114333972B (zh) * | 2020-09-30 | 2023-09-01 | 长鑫存储技术有限公司 | 自刷新周期测试方法及装置 |
| KR20230135913A (ko) * | 2022-03-17 | 2023-09-26 | 에스케이하이닉스 주식회사 | 메모리 및 메모리의 동작 방법 |
Family Cites Families (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5262998A (en) * | 1991-08-14 | 1993-11-16 | Micron Technology, Inc. | Dynamic random access memory with operational sleep mode |
| JPH05334870A (ja) * | 1992-06-02 | 1993-12-17 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JP2980463B2 (ja) * | 1992-09-28 | 1999-11-22 | シャープ株式会社 | 半導体メモリ装置の駆動方法 |
| JPH0765571A (ja) * | 1993-08-27 | 1995-03-10 | Nec Corp | 半導体記憶装置 |
| US5594699A (en) * | 1993-09-20 | 1997-01-14 | Fujitsu Limited | DRAM with reduced electric power consumption |
| KR960006285B1 (ko) | 1993-12-18 | 1996-05-13 | 삼성전자주식회사 | 반도체 메모리 장치의 셀프 리프레시 방법 및 그 회로 |
| JP3759758B2 (ja) * | 1994-02-03 | 2006-03-29 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP3725911B2 (ja) * | 1994-06-02 | 2005-12-14 | 株式会社ルネサステクノロジ | 半導体装置 |
| JPH0822693A (ja) * | 1994-07-05 | 1996-01-23 | Fujitsu Ltd | 半導体記憶装置 |
| JP3182071B2 (ja) * | 1995-02-08 | 2001-07-03 | 松下電器産業株式会社 | 半導体記憶回路のデータ保持時間の延長装置及び延長方法 |
| TW306001B (de) * | 1995-02-08 | 1997-05-21 | Matsushita Electric Industrial Co Ltd | |
| US5627791A (en) | 1996-02-16 | 1997-05-06 | Micron Technology, Inc. | Multiple bank memory with auto refresh to specified bank |
| KR100231602B1 (ko) * | 1996-11-08 | 1999-11-15 | 김영환 | 복합 모드형 기판전압 발생회로 |
| US6021063A (en) * | 1997-01-13 | 2000-02-01 | Vanguard International Semiconductor Corporation | Method and structure for improving data retention in a DRAM |
| JP3695902B2 (ja) * | 1997-06-24 | 2005-09-14 | 富士通株式会社 | 半導体記憶装置 |
| KR100281280B1 (ko) | 1997-06-30 | 2001-03-02 | 김영환 | 반도체 메모리 소자의 셀 플레이트 전압 발생장치 |
| KR100253305B1 (ko) * | 1997-08-05 | 2000-04-15 | 김영환 | 긴 리프레쉬간격을 갖는 메모리셀 제어방법 |
| JPH1186536A (ja) * | 1997-09-12 | 1999-03-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100252048B1 (ko) * | 1997-11-18 | 2000-05-01 | 윤종용 | 반도체 메모리장치의 데이터 마스킹 회로 및 데이터 마스킹방법 |
| TW426847B (en) * | 1998-05-21 | 2001-03-21 | Nippon Electric Co | Semiconductor memory device capable of securing large latch margin |
| DE19839105B4 (de) * | 1998-08-27 | 2006-04-06 | Infineon Technologies Ag | Integrierter Halbleiterspeicher mit Steuerungseinrichtung zum taktsynchronen Schreiben und Lesen |
| KR100306882B1 (ko) * | 1998-10-28 | 2001-12-01 | 박종섭 | 반도체메모리소자에서데이터스트로브신호를버퍼링하기위한방법및장치 |
| KR100303775B1 (ko) * | 1998-10-28 | 2001-09-24 | 박종섭 | 디디알 에스디램에서 데이터스트로브신호를 제어하기 위한 방법및 장치 |
| US6081477A (en) * | 1998-12-03 | 2000-06-27 | Micron Technology, Inc. | Write scheme for a double data rate SDRAM |
| JP2000348488A (ja) * | 1999-06-08 | 2000-12-15 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100296913B1 (ko) * | 1999-06-28 | 2001-07-12 | 박종섭 | 반도체메모리장치의 데이터스트로브신호 출력버퍼 |
| KR100299181B1 (ko) * | 1999-07-15 | 2001-11-01 | 윤종용 | 반도체 메모리 장치 및 이 장치의 라이트 데이터 마스킹 방법 |
| JP2001052476A (ja) * | 1999-08-05 | 2001-02-23 | Mitsubishi Electric Corp | 半導体装置 |
| US6407963B1 (en) * | 1999-10-19 | 2002-06-18 | Hitachi, Ltd. | Semiconductor memory device of DDR configuration having improvement in glitch immunity |
| US6466491B2 (en) * | 2000-05-19 | 2002-10-15 | Fujitsu Limited | Memory system and memory controller with reliable data latch operation |
| US6760856B1 (en) * | 2000-07-17 | 2004-07-06 | International Business Machines Corporation | Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration |
| US6529993B1 (en) * | 2000-10-12 | 2003-03-04 | International Business Machines Corp. | Data and data strobe circuits and operating protocol for double data rate memories |
| US6728162B2 (en) * | 2001-03-05 | 2004-04-27 | Samsung Electronics Co. Ltd | Data input circuit and method for synchronous semiconductor memory device |
| JP2003068077A (ja) * | 2001-08-28 | 2003-03-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
| DE10154613B4 (de) * | 2001-11-07 | 2006-11-23 | Infineon Technologies Ag | Verfahren zum Vorladen von Speicherzellen eines dynamischen Halbleiterspeichers beim Power Up sowie Halbleiterspeicher |
| JP2003249077A (ja) * | 2002-02-21 | 2003-09-05 | Elpida Memory Inc | 半導体記憶装置及びその制御方法 |
| JP2004030738A (ja) * | 2002-06-24 | 2004-01-29 | Toshiba Corp | ダイナミック型半導体メモリ装置 |
| US6819599B2 (en) * | 2002-08-01 | 2004-11-16 | Micron Technology, Inc. | Programmable DQS preamble |
| US6760261B2 (en) * | 2002-09-25 | 2004-07-06 | Infineon Technologies Ag | DQS postamble noise suppression by forcing a minimum pulse length |
| US6961277B2 (en) * | 2003-07-08 | 2005-11-01 | Micron Technology, Inc. | Method of refreshing a PCRAM memory device |
| US6922367B2 (en) | 2003-07-09 | 2005-07-26 | Micron Technology, Inc. | Data strobe synchronization circuit and method for double data rate, multi-bit writes |
| US7031205B2 (en) | 2003-09-29 | 2006-04-18 | Infineon Technologies North America Corp. | Random access memory with post-amble data strobe signal noise rejection |
| US20050105372A1 (en) * | 2003-10-30 | 2005-05-19 | Fujitsu Limited | Semiconductor memory |
| US7082073B2 (en) | 2004-12-03 | 2006-07-25 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
| US7280417B2 (en) | 2005-04-26 | 2007-10-09 | Micron Technology, Inc. | System and method for capturing data signals using a data strobe signal |
| US20070028027A1 (en) | 2005-07-26 | 2007-02-01 | Micron Technology, Inc. | Memory device and method having separate write data and read data buses |
| KR100753048B1 (ko) * | 2005-09-05 | 2007-08-30 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 주변영역 전압 발생 장치 |
| JP4936421B2 (ja) | 2005-09-14 | 2012-05-23 | エルピーダメモリ株式会社 | Ｄｒａｍ、入力制御回路、及び入力制御方法 |
-
2004
- 2004-12-03 US US11/003,547 patent/US7082073B2/en not_active Expired - Lifetime
-
2005
- 2005-11-22 CN CN2005800411671A patent/CN101069062B/zh not_active Expired - Lifetime
- 2005-11-22 KR KR1020077015262A patent/KR100887527B1/ko not_active Expired - Lifetime
- 2005-11-22 EP EP05852054A patent/EP1828716B1/de not_active Expired - Lifetime
- 2005-11-22 JP JP2007544397A patent/JP4979589B2/ja not_active Expired - Fee Related
- 2005-11-22 DE DE602005027898T patent/DE602005027898D1/de not_active Expired - Lifetime
- 2005-11-22 AT AT05852054T patent/ATE508459T1/de not_active IP Right Cessation
- 2005-11-22 WO PCT/US2005/042420 patent/WO2006060249A1/en not_active Ceased
-
2006
- 2006-05-08 US US11/430,379 patent/US7408828B1/en not_active Expired - Lifetime
-
2008
- 2008-04-11 US US12/082,579 patent/US7995415B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7995415B2 (en) | 2011-08-09 |
| CN101069062B (zh) | 2010-09-08 |
| KR20070091638A (ko) | 2007-09-11 |
| US20080192557A1 (en) | 2008-08-14 |
| EP1828716A4 (de) | 2008-10-08 |
| US7082073B2 (en) | 2006-07-25 |
| EP1828716B1 (de) | 2011-05-04 |
| CN101069062A (zh) | 2007-11-07 |
| DE602005027898D1 (de) | 2011-06-16 |
| WO2006060249A1 (en) | 2006-06-08 |
| US7408828B1 (en) | 2008-08-05 |
| JP4979589B2 (ja) | 2012-07-18 |
| KR100887527B1 (ko) | 2009-03-09 |
| EP1828716A1 (de) | 2007-09-05 |
| JP2008522346A (ja) | 2008-06-26 |
| US20060120193A1 (en) | 2006-06-08 |
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| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |