ATE508474T1 - Übertragungsleitungen mit einstellbarer impedanz in einer weiterverteilungsschicht - Google Patents

Übertragungsleitungen mit einstellbarer impedanz in einer weiterverteilungsschicht

Info

Publication number
ATE508474T1
ATE508474T1 AT02780619T AT02780619T ATE508474T1 AT E508474 T1 ATE508474 T1 AT E508474T1 AT 02780619 T AT02780619 T AT 02780619T AT 02780619 T AT02780619 T AT 02780619T AT E508474 T1 ATE508474 T1 AT E508474T1
Authority
AT
Austria
Prior art keywords
transmission line
distance
transmission lines
return path
impedance
Prior art date
Application number
AT02780619T
Other languages
English (en)
Inventor
Surasit Chungpaibonnpatana
Hassan Hashemi
Siamak Fazelpour
Original Assignee
Skyworks Solutions Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Skyworks Solutions Inc filed Critical Skyworks Solutions Inc
Application granted granted Critical
Publication of ATE508474T1 publication Critical patent/ATE508474T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/401—Resistive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Waveguides (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Communication Cables (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT02780619T 2001-11-13 2002-11-12 Übertragungsleitungen mit einstellbarer impedanz in einer weiterverteilungsschicht ATE508474T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/012,812 US6674174B2 (en) 2001-11-13 2001-11-13 Controlled impedance transmission lines in a redistribution layer
PCT/US2002/036207 WO2003043083A1 (en) 2001-11-13 2002-11-12 Controlled impedance transmission lines in a redistribution layer

Publications (1)

Publication Number Publication Date
ATE508474T1 true ATE508474T1 (de) 2011-05-15

Family

ID=21756804

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02780619T ATE508474T1 (de) 2001-11-13 2002-11-12 Übertragungsleitungen mit einstellbarer impedanz in einer weiterverteilungsschicht

Country Status (7)

Country Link
US (1) US6674174B2 (de)
EP (1) EP1444731B1 (de)
KR (1) KR100534048B1 (de)
CN (1) CN100336213C (de)
AT (1) ATE508474T1 (de)
DE (1) DE60239950D1 (de)
WO (1) WO2003043083A1 (de)

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US6822327B1 (en) * 2003-06-13 2004-11-23 Delphi Technologies, Inc. Flip-chip interconnected with increased current-carrying capability
US7098518B1 (en) * 2003-08-27 2006-08-29 National Semiconductor Corporation Die-level opto-electronic device and method of making same
US7342312B2 (en) * 2004-09-29 2008-03-11 Rohm Co., Ltd. Semiconductor device
DE102005002707B4 (de) * 2005-01-19 2007-07-26 Infineon Technologies Ag Verfahren zur Herstellung elektrischer Verbindungen in einem Halbleiterbauteil mittels koaxialer Mikroverbindungselemente
US7541251B2 (en) * 2006-02-10 2009-06-02 California Micro Devices Wire bond and redistribution layer process
US8946873B2 (en) 2007-08-28 2015-02-03 Micron Technology, Inc. Redistribution structures for microfeature workpieces
CN102027633B (zh) * 2008-06-24 2014-11-05 国际商业机器公司 用于提供具有固定特性阻抗的片上可变延迟传输线的设计结构、结构和方法
US8193878B2 (en) 2008-06-24 2012-06-05 International Business Machines Corporation Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance
US8138857B2 (en) 2008-06-24 2012-03-20 International Business Machines Corporation Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance
CN102099957B (zh) * 2008-07-15 2014-10-22 松下电器产业株式会社 慢波传输线路
US8659170B2 (en) * 2010-01-20 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
KR101685057B1 (ko) * 2010-01-22 2016-12-09 삼성전자주식회사 반도체 소자의 적층 패키지
KR101666192B1 (ko) 2010-02-02 2016-10-14 삼성전자 주식회사 반도체 칩 및 이를 포함하는 반도체 모듈
CN102469679A (zh) * 2010-11-05 2012-05-23 富士康(昆山)电脑接插件有限公司 印刷电路板
US9171798B2 (en) 2013-01-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for transmission lines in packages
US9711471B2 (en) 2015-11-18 2017-07-18 Nxp Usa, Inc. Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology
JP6798252B2 (ja) * 2016-10-31 2020-12-09 住友電気工業株式会社 高周波装置
KR20220019331A (ko) 2020-08-10 2022-02-17 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
US12699114B2 (en) 2024-06-04 2026-08-04 Menlo Microsystems, Inc. Probe card design for optimal current distribution

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
US4498122A (en) 1982-12-29 1985-02-05 At&T Bell Laboratories High-speed, high pin-out LSI chip package
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
JP3142723B2 (ja) * 1994-09-21 2001-03-07 シャープ株式会社 半導体装置及びその製造方法
JP2546192B2 (ja) * 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
KR100218996B1 (ko) * 1995-03-24 1999-09-01 모기 쥰이찌 반도체장치
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
JP3608205B2 (ja) * 1996-10-17 2005-01-05 セイコーエプソン株式会社 半導体装置及びその製造方法並びに回路基板
JP2982738B2 (ja) 1997-04-04 1999-11-29 日本電気株式会社 セラミック・チップサイズパッケージの構造
JP3335575B2 (ja) * 1997-06-06 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
JP3152180B2 (ja) * 1997-10-03 2001-04-03 日本電気株式会社 半導体装置及びその製造方法
US6025647A (en) * 1997-11-24 2000-02-15 Vlsi Technology, Inc. Apparatus for equalizing signal parameters in flip chip redistribution layers
US6248429B1 (en) * 1998-07-06 2001-06-19 Micron Technology, Inc. Metallized recess in a substrate
US5994766A (en) * 1998-09-21 1999-11-30 Vlsi Technology, Inc. Flip chip circuit arrangement with redistribution layer that minimizes crosstalk
JP2000138313A (ja) * 1998-10-30 2000-05-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6078100A (en) * 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
US6407450B1 (en) * 1999-07-15 2002-06-18 Altera Corporation Semiconductor package with universal substrate for electrically interfacing with different sized chips that have different logic functions
US6249047B1 (en) * 1999-09-02 2001-06-19 Micron Technology, Inc. Ball array layout
JP4301661B2 (ja) * 1999-11-12 2009-07-22 富士通マイクロエレクトロニクス株式会社 ボールグリッドアレイ構造のデバイスに使用されるコンタクトフィルム及びデバイス実装構造体
JP3578964B2 (ja) * 2000-03-21 2004-10-20 富士通株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR100534048B1 (ko) 2005-12-06
DE60239950D1 (de) 2011-06-16
CN100336213C (zh) 2007-09-05
EP1444731A4 (de) 2005-04-06
KR20050044326A (ko) 2005-05-12
CN1599957A (zh) 2005-03-23
EP1444731A1 (de) 2004-08-11
US20030193078A1 (en) 2003-10-16
US6674174B2 (en) 2004-01-06
WO2003043083A1 (en) 2003-05-22
EP1444731B1 (de) 2011-05-04

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