ATE51109T1 - Elektrische duennschichtverbindungen fuer integrierte schaltungen. - Google Patents

Elektrische duennschichtverbindungen fuer integrierte schaltungen.

Info

Publication number
ATE51109T1
ATE51109T1 AT85308479T AT85308479T ATE51109T1 AT E51109 T1 ATE51109 T1 AT E51109T1 AT 85308479 T AT85308479 T AT 85308479T AT 85308479 T AT85308479 T AT 85308479T AT E51109 T1 ATE51109 T1 AT E51109T1
Authority
AT
Austria
Prior art keywords
interconnect lines
thin
integrated circuits
interconnect
metallic
Prior art date
Application number
AT85308479T
Other languages
English (en)
Inventor
Peter L Young
Jay Cech
Kin Li
Original Assignee
Gould Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gould Inc filed Critical Gould Inc
Application granted granted Critical
Publication of ATE51109T1 publication Critical patent/ATE51109T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/241—Reinforcing of the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing of the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT85308479T 1985-01-31 1985-11-21 Elektrische duennschichtverbindungen fuer integrierte schaltungen. ATE51109T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/697,092 US4705606A (en) 1985-01-31 1985-01-31 Thin-film electrical connections for integrated circuits
EP85308479A EP0190490B1 (de) 1985-01-31 1985-11-21 Elektrische Dünnschichtverbindungen für integrierte Schaltungen

Publications (1)

Publication Number Publication Date
ATE51109T1 true ATE51109T1 (de) 1990-03-15

Family

ID=24799756

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85308479T ATE51109T1 (de) 1985-01-31 1985-11-21 Elektrische duennschichtverbindungen fuer integrierte schaltungen.

Country Status (5)

Country Link
US (1) US4705606A (de)
EP (1) EP0190490B1 (de)
JP (1) JPS61182245A (de)
AT (1) ATE51109T1 (de)
DE (1) DE3576611D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3627417A1 (de) * 1986-08-13 1988-02-18 Siemens Ag Verfahren zum herstellen von niederohmigen verbindungen in der isolationsschicht zwischen zwei metallisierungsebenen
EP0286854A1 (de) * 1987-04-13 1988-10-19 Oerlikon-Contraves AG Verfahren zum Herstellen einer mehrlagigen Dünnschichstschaltung
US5086500A (en) * 1987-08-07 1992-02-04 Tektronix, Inc. Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
DE3851335D1 (de) * 1988-12-05 1994-10-06 Heinz Karl Diedrich Vakuumbehälter zum kryogenischen Kühlen einer Packung für eine elektronische Anordnung.
US4980034A (en) * 1989-04-04 1990-12-25 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for TAB
US5106461A (en) * 1989-04-04 1992-04-21 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for tab
US5182420A (en) * 1989-04-25 1993-01-26 Cray Research, Inc. Method of fabricating metallized chip carriers from wafer-shaped substrates
US5317194A (en) * 1989-10-17 1994-05-31 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device having intermediate silicon thermal dissipation means and embedded heat sink
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
JPH07123133B2 (ja) * 1990-08-13 1995-12-25 株式会社東芝 フィルムキャリア構造
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
WO1992009102A1 (en) * 1990-11-15 1992-05-29 International Business Machines Corporation A method of making a multilayer thin film structure
US5196377A (en) * 1990-12-20 1993-03-23 Cray Research, Inc. Method of fabricating silicon-based carriers
US5442237A (en) * 1991-10-21 1995-08-15 Motorola Inc. Semiconductor device having a low permittivity dielectric
US5220487A (en) * 1992-01-27 1993-06-15 International Business Machines Corporation Electronic package with enhanced heat sinking
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
US5305186A (en) * 1993-01-27 1994-04-19 International Business Machines Corporation Power carrier with selective thermal performance
US5391914A (en) * 1994-03-16 1995-02-21 The United States Of America As Represented By The Secretary Of The Navy Diamond multilayer multichip module substrate
DE59510873D1 (de) 1994-06-27 2004-04-22 Infineon Technologies Ag Verbindungs- und Aufbautechnik für Multichip-Module
JP2817664B2 (ja) * 1995-04-24 1998-10-30 日本電気株式会社 半導体装置の製造方法
US5986340A (en) * 1996-05-02 1999-11-16 National Semiconductor Corporation Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same
US6034425A (en) * 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
US20020000380A1 (en) * 1999-10-28 2002-01-03 Lyndon W. Graham Method, chemistry, and apparatus for noble metal electroplating on a microelectronic workpiece
US7977037B2 (en) * 2006-08-24 2011-07-12 Micron Technology, Inc. Photoresist processing methods

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2042059A5 (de) * 1969-04-02 1971-02-05 Ibm
US3876460A (en) * 1974-01-24 1975-04-08 Plessey Inc Fine-line thick-film substrate fabrication
US4134125A (en) * 1977-07-20 1979-01-09 Bell Telephone Laboratories, Incorporated Passivation of metallized semiconductor substrates
US4210885A (en) * 1978-06-30 1980-07-01 International Business Machines Corporation Thin film lossy line for preventing reflections in microcircuit chip package interconnections
DE2945385A1 (de) * 1978-11-09 1980-05-14 Maruman Integrated Circuits In Halbleiter-anordnung und verfahren zu ihrer herstellung
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4254445A (en) * 1979-05-07 1981-03-03 International Business Machines Corporation Discretionary fly wire chip interconnection
US4349862A (en) * 1980-08-11 1982-09-14 International Business Machines Corporation Capacitive chip carrier and multilayer ceramic capacitors
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4336320A (en) * 1981-03-12 1982-06-22 Honeywell Inc. Process for dielectric stenciled microcircuits
JPS57170524A (en) * 1981-04-15 1982-10-20 Toshiba Corp Manufacture of semiconductor device
JPS57177537A (en) * 1981-04-24 1982-11-01 Matsushita Electric Ind Co Ltd Isolation of semiconductor element
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
US4430690A (en) * 1982-10-07 1984-02-07 International Business Machines Corporation Low inductance MLC capacitor with metal impregnation and solder bar contact

Also Published As

Publication number Publication date
JPS61182245A (ja) 1986-08-14
EP0190490A3 (en) 1987-01-28
EP0190490B1 (de) 1990-03-14
EP0190490A2 (de) 1986-08-13
US4705606A (en) 1987-11-10
DE3576611D1 (de) 1990-04-19

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
EEIH Change in the person of patent owner
EEIH Change in the person of patent owner
REN Ceased due to non-payment of the annual fee