ATE511703T1 - Herstellungsverfahren für durchkontakte - Google Patents

Herstellungsverfahren für durchkontakte

Info

Publication number
ATE511703T1
ATE511703T1 AT07709445T AT07709445T ATE511703T1 AT E511703 T1 ATE511703 T1 AT E511703T1 AT 07709445 T AT07709445 T AT 07709445T AT 07709445 T AT07709445 T AT 07709445T AT E511703 T1 ATE511703 T1 AT E511703T1
Authority
AT
Austria
Prior art keywords
wafer
connections
low resistivity
front side
layer
Prior art date
Application number
AT07709445T
Other languages
English (en)
Inventor
Edvard Kaelvesten
Tomas Bauer
Thorbjoern Ebefors
Original Assignee
Silex Microsystems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silex Microsystems Ab filed Critical Silex Microsystems Ab
Application granted granted Critical
Publication of ATE511703T1 publication Critical patent/ATE511703T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4451—Semiconductor materials, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H10W70/662—Semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
AT07709445T 2006-02-01 2007-01-31 Herstellungsverfahren für durchkontakte ATE511703T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE0600214 2006-02-01
PCT/SE2007/050052 WO2007089206A1 (en) 2006-02-01 2007-01-31 Vias and method of making

Publications (1)

Publication Number Publication Date
ATE511703T1 true ATE511703T1 (de) 2011-06-15

Family

ID=38327689

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07709445T ATE511703T1 (de) 2006-02-01 2007-01-31 Herstellungsverfahren für durchkontakte

Country Status (5)

Country Link
US (2) US8324103B2 (de)
EP (2) EP2005467B1 (de)
AT (1) ATE511703T1 (de)
SE (2) SE1050461A1 (de)
WO (2) WO2007089207A1 (de)

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US8049310B2 (en) * 2008-04-01 2011-11-01 Qimonda Ag Semiconductor device with an interconnect element and method for manufacture
WO2009153728A1 (en) * 2008-06-16 2009-12-23 Nxp B.V. Through wafer via filling method
NO20083766L (no) 2008-09-01 2010-03-02 Idex Asa Overflatesensor
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SE534510C2 (sv) 2008-11-19 2011-09-13 Silex Microsystems Ab Funktionell inkapsling
US8729713B2 (en) 2008-12-23 2014-05-20 Silex Microsystems Ab Via structure and method thereof
US8630033B2 (en) 2008-12-23 2014-01-14 Silex Microsystems Ab Via structure and method thereof
SE533992C2 (sv) 2008-12-23 2011-03-22 Silex Microsystems Ab Elektrisk anslutning i en struktur med isolerande och ledande lager
US8426233B1 (en) 2009-01-09 2013-04-23 Integrated Device Technology, Inc. Methods of packaging microelectromechanical resonators
TW201032389A (en) * 2009-02-20 2010-09-01 Aiconn Technology Corp Wireless transceiver module
US8053898B2 (en) * 2009-10-05 2011-11-08 Samsung Electronics Co., Ltd. Connection for off-chip electrostatic discharge protection
NO20093601A1 (no) 2009-12-29 2011-06-30 Idex Asa Overflatesensor
DE102010029760B4 (de) 2010-06-07 2019-02-21 Robert Bosch Gmbh Bauelement mit einer Durchkontaktierung und Verfahren zu seiner Herstellung
WO2012069078A1 (de) * 2010-11-23 2012-05-31 Robert Bosch Gmbh Eutektische bondung von dünnchips auf einem trägersubstrat
SE536530C2 (sv) * 2011-04-21 2014-02-04 Silex Microsystems Ab Startsubstrat för halvledarteknologi med substratgenomgåendekopplingar och en metod för tillverkning därav
US8803269B2 (en) 2011-05-05 2014-08-12 Cisco Technology, Inc. Wafer scale packaging platform for transceivers
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
US9029259B2 (en) * 2012-02-17 2015-05-12 Teledyne Scientific & Imaging, Llc Self-aligning hybridization method
SE538069C2 (sv) 2012-03-12 2016-02-23 Silex Microsystems Ab Metod att tillverka tätpackade viastrukturer med routing iplanet
SE538058C2 (sv) 2012-03-30 2016-02-23 Silex Microsystems Ab Metod att tillhandahålla ett viahål och en routing-struktur
US9102517B2 (en) 2012-08-22 2015-08-11 International Business Machines Corporation Semiconductor structures provided within a cavity and related design structures
SE538062C2 (sv) 2012-09-27 2016-02-23 Silex Microsystems Ab Kemiskt pläterad metallvia genom kisel
DE102013208816A1 (de) 2013-05-14 2014-11-20 Robert Bosch Gmbh Verfahren zum Erzeugen eines Durchkontakts in einem CMOS-Substrat
KR102245134B1 (ko) 2014-04-18 2021-04-28 삼성전자 주식회사 반도체 칩을 구비하는 반도체 패키지
US12009225B2 (en) 2018-03-30 2024-06-11 Samtec, Inc. Electrically conductive vias and methods for producing same
EP3876258A1 (de) * 2020-03-06 2021-09-08 ASML Netherlands B.V. Strahlmanipulator in einer ladungsteilchenstrahl-belichtungsvorrichtung
WO2022217146A1 (en) 2021-04-09 2022-10-13 Samtec, Inc. High aspect ratio vias filled with liquid metal fill
US20250070009A1 (en) * 2021-12-28 2025-02-27 Medtronic, Inc. Electrical component and method of forming same
EP4457855A1 (de) * 2021-12-28 2024-11-06 Medtronic, Inc. Elektrisches bauelement und verfahren zu dessen herstellung

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Also Published As

Publication number Publication date
EP2005467B1 (de) 2018-07-11
EP1987535A1 (de) 2008-11-05
US9312217B2 (en) 2016-04-12
US20100052107A1 (en) 2010-03-04
EP2005467A1 (de) 2008-12-24
US20090195948A1 (en) 2009-08-06
US8324103B2 (en) 2012-12-04
EP2005467A4 (de) 2011-05-18
SE0801620L (sv) 2008-10-30
EP1987535B1 (de) 2011-06-01
WO2007089206A1 (en) 2007-08-09
SE533308C2 (sv) 2010-08-24
SE1050461A1 (sv) 2010-05-10
WO2007089207A1 (en) 2007-08-09

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties