ATE513264T1 - Direktzugriffsspeichersystem mit destruktivem lesen, gepuffert mit einem speicher-cache mit destruktivem lesen - Google Patents

Direktzugriffsspeichersystem mit destruktivem lesen, gepuffert mit einem speicher-cache mit destruktivem lesen

Info

Publication number
ATE513264T1
ATE513264T1 AT03728351T AT03728351T ATE513264T1 AT E513264 T1 ATE513264 T1 AT E513264T1 AT 03728351 T AT03728351 T AT 03728351T AT 03728351 T AT03728351 T AT 03728351T AT E513264 T1 ATE513264 T1 AT E513264T1
Authority
AT
Austria
Prior art keywords
destructive read
direct access
access memory
cache
memory system
Prior art date
Application number
AT03728351T
Other languages
English (en)
Inventor
Brian L Ji
Chorng-Lii Hwang
Toshiaki K Kirihata
Seiji Munetoh
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE513264T1 publication Critical patent/ATE513264T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
AT03728351T 2002-04-25 2003-04-07 Direktzugriffsspeichersystem mit destruktivem lesen, gepuffert mit einem speicher-cache mit destruktivem lesen ATE513264T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/063,466 US6801980B2 (en) 2002-04-25 2002-04-25 Destructive-read random access memory system buffered with destructive-read memory cache
PCT/US2003/010746 WO2003091883A1 (en) 2002-04-25 2003-04-07 Destructive-read random access memory system buffered with destructive-read memory cache

Publications (1)

Publication Number Publication Date
ATE513264T1 true ATE513264T1 (de) 2011-07-15

Family

ID=29248086

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03728351T ATE513264T1 (de) 2002-04-25 2003-04-07 Direktzugriffsspeichersystem mit destruktivem lesen, gepuffert mit einem speicher-cache mit destruktivem lesen

Country Status (10)

Country Link
US (3) US6801980B2 (de)
EP (1) EP1497733B1 (de)
JP (1) JP4150718B2 (de)
KR (1) KR100772998B1 (de)
CN (1) CN1296832C (de)
AT (1) ATE513264T1 (de)
AU (1) AU2003234695A1 (de)
IL (1) IL164726A0 (de)
TW (1) TW594740B (de)
WO (1) WO2003091883A1 (de)

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US20040221117A1 (en) * 2003-05-02 2004-11-04 Shelor Charles F. Logic and method for reading data from cache
US20050114588A1 (en) * 2003-11-26 2005-05-26 Lucker Jonathan C. Method and apparatus to improve memory performance
JP2006190402A (ja) * 2005-01-07 2006-07-20 Renesas Technology Corp 半導体装置
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US8433880B2 (en) * 2009-03-17 2013-04-30 Memoir Systems, Inc. System and method for storing data in a virtualized high speed memory system
US8266408B2 (en) * 2009-03-17 2012-09-11 Memoir Systems, Inc. System and method for storing data in a virtualized high speed memory system
US9442846B2 (en) 2009-03-17 2016-09-13 Cisco Technology, Inc. High speed memory systems and methods for designing hierarchical memory systems
WO2011075167A1 (en) * 2009-12-15 2011-06-23 Memoir Systems,Inc. System and method for reduced latency caching
WO2011154780A1 (en) * 2010-06-11 2011-12-15 Freescale Semiconductor, Inc. Method for providing data protection for data stored within a memory element and integrated circuit device therefor
US8811071B2 (en) 2011-01-31 2014-08-19 Everspin Technologies, Inc. Method of writing to a spin torque magnetic random access memory
US8675442B2 (en) 2011-10-04 2014-03-18 Qualcomm Incorporated Energy efficient memory with reconfigurable decoding
CN104484239B (zh) * 2014-12-05 2019-02-26 深圳市华宝电子科技有限公司 一种车载视频文件修复方法及装置
US10866897B2 (en) * 2016-09-26 2020-12-15 Samsung Electronics Co., Ltd. Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer
US10650899B2 (en) * 2017-04-27 2020-05-12 Everspin Technologies, Inc. Delayed write-back in memory with calibration support
JP2019079377A (ja) 2017-10-26 2019-05-23 東芝メモリ株式会社 半導体記憶装置
KR102683747B1 (ko) 2019-01-22 2024-07-11 에스케이하이닉스 주식회사 반도체 메모리 장치
US11899590B2 (en) * 2021-06-18 2024-02-13 Seagate Technology Llc Intelligent cache with read destructive memory cells

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Also Published As

Publication number Publication date
TW594740B (en) 2004-06-21
CN1296832C (zh) 2007-01-24
WO2003091883A1 (en) 2003-11-06
US20030204667A1 (en) 2003-10-30
AU2003234695A1 (en) 2003-11-10
EP1497733A1 (de) 2005-01-19
US20050226083A1 (en) 2005-10-13
US20040221097A1 (en) 2004-11-04
KR20040105805A (ko) 2004-12-16
CN1650270A (zh) 2005-08-03
EP1497733B1 (de) 2011-06-15
KR100772998B1 (ko) 2007-11-05
US7203794B2 (en) 2007-04-10
IL164726A0 (en) 2005-12-18
JP2005524146A (ja) 2005-08-11
TW200305882A (en) 2003-11-01
EP1497733A4 (de) 2008-04-30
JP4150718B2 (ja) 2008-09-17
US6801980B2 (en) 2004-10-05
US6948028B2 (en) 2005-09-20

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