ATE515795T1 - Verfahren zur herstellung einer vorgespannten schicht - Google Patents

Verfahren zur herstellung einer vorgespannten schicht

Info

Publication number
ATE515795T1
ATE515795T1 AT09155871T AT09155871T ATE515795T1 AT E515795 T1 ATE515795 T1 AT E515795T1 AT 09155871 T AT09155871 T AT 09155871T AT 09155871 T AT09155871 T AT 09155871T AT E515795 T1 ATE515795 T1 AT E515795T1
Authority
AT
Austria
Prior art keywords
layer
substrate
assembling
stress
magnetic field
Prior art date
Application number
AT09155871T
Other languages
English (en)
Inventor
Chrystel Deguet
Frank Fournel
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE515795T1 publication Critical patent/ATE515795T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Micromachines (AREA)
  • Laminated Bodies (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Heating, Cooling, Or Curing Plastics Or The Like In General (AREA)
AT09155871T 2008-03-28 2009-03-23 Verfahren zur herstellung einer vorgespannten schicht ATE515795T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0852034A FR2929447B1 (fr) 2008-03-28 2008-03-28 Procede de realisation d'une couche contrainte

Publications (1)

Publication Number Publication Date
ATE515795T1 true ATE515795T1 (de) 2011-07-15

Family

ID=39944250

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09155871T ATE515795T1 (de) 2008-03-28 2009-03-23 Verfahren zur herstellung einer vorgespannten schicht

Country Status (5)

Country Link
US (1) US7863156B2 (de)
EP (1) EP2105958B1 (de)
JP (1) JP5731104B2 (de)
AT (1) ATE515795T1 (de)
FR (1) FR2929447B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3040108B1 (fr) 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
DE102015216997A1 (de) * 2015-09-04 2017-03-09 Robert Bosch Gmbh Kapazitive Struktur und Verfahren zum Bestimmen einer Ladungsmenge unter Verwendung der kapazitiven Struktur
US12453287B2 (en) 2019-06-03 2025-10-21 Gregory Scott Fischer Optical actuator
FR3108788B1 (fr) * 2020-03-24 2026-01-23 Soitec Silicon On Insulator Procédé de fabrication d’une structure piézoélectrique pour dispositif radiofréquence et pouvant servir pour le transfert d’une couche piézoélectrique, et procédé de transfert d’une telle couche piézoélectrique

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0818115A (ja) * 1994-07-04 1996-01-19 Matsushita Electric Ind Co Ltd 複合圧電デバイス
US5834882A (en) * 1996-12-11 1998-11-10 Face International Corp. Multi-layer piezoelectric transformer
JP2000277715A (ja) * 1999-03-25 2000-10-06 Matsushita Electric Ind Co Ltd 半導体基板，その製造方法及び半導体装置
US6603156B2 (en) * 2001-03-31 2003-08-05 International Business Machines Corporation Strained silicon on insulator structures
US6614144B2 (en) * 2001-10-04 2003-09-02 Force International, Corp. Multilayer piezoelectric transformer
US6767749B2 (en) * 2002-04-22 2004-07-27 The United States Of America As Represented By The Secretary Of The Navy Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US6992025B2 (en) * 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
WO2006097522A1 (en) * 2005-03-18 2006-09-21 Bae Systems Plc An actuator
JP4630733B2 (ja) * 2005-05-31 2011-02-09 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
US20090246933A1 (en) 2009-10-01
FR2929447A1 (fr) 2009-10-02
EP2105958A1 (de) 2009-09-30
JP2009246366A (ja) 2009-10-22
JP5731104B2 (ja) 2015-06-10
FR2929447B1 (fr) 2010-05-28
EP2105958B1 (de) 2011-07-06
US7863156B2 (en) 2011-01-04

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