ATE516547T1 - Brücke, prozessoreinheit, informationsverarbeitungsvorrichtung und zugangskontrollverfahren - Google Patents

Brücke, prozessoreinheit, informationsverarbeitungsvorrichtung und zugangskontrollverfahren

Info

Publication number
ATE516547T1
ATE516547T1 AT07706612T AT07706612T ATE516547T1 AT E516547 T1 ATE516547 T1 AT E516547T1 AT 07706612 T AT07706612 T AT 07706612T AT 07706612 T AT07706612 T AT 07706612T AT E516547 T1 ATE516547 T1 AT E516547T1
Authority
AT
Austria
Prior art keywords
address
peripheral device
access
processor unit
identification information
Prior art date
Application number
AT07706612T
Other languages
English (en)
Inventor
Hideyuki Saito
Takeshi Yamazaki
Yuji Takahashi
Hideki Mitsubayashi
Original Assignee
Sony Corp
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sony Computer Entertainment Inc filed Critical Sony Corp
Application granted granted Critical
Publication of ATE516547T1 publication Critical patent/ATE516547T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Bridges Or Land Bridges (AREA)
  • Selective Calling Equipment (AREA)
AT07706612T 2006-04-06 2007-01-11 Brücke, prozessoreinheit, informationsverarbeitungsvorrichtung und zugangskontrollverfahren ATE516547T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006105735 2006-04-06
JP2006121900 2006-04-26
PCT/JP2007/050265 WO2007129482A1 (ja) 2006-04-06 2007-01-11 ブリッジ、プロセッサユニット、情報処理装置およびアクセス制御方法

Publications (1)

Publication Number Publication Date
ATE516547T1 true ATE516547T1 (de) 2011-07-15

Family

ID=38667594

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07706612T ATE516547T1 (de) 2006-04-06 2007-01-11 Brücke, prozessoreinheit, informationsverarbeitungsvorrichtung und zugangskontrollverfahren

Country Status (6)

Country Link
US (1) US8006000B2 (de)
EP (1) EP1903443B1 (de)
JP (1) JP4219964B2 (de)
CN (1) CN101326501B (de)
AT (1) ATE516547T1 (de)
WO (1) WO2007129482A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4514798B2 (ja) * 2005-09-29 2010-07-28 パイオニア株式会社 中継装置及び中継方法並びに中継処理用プログラム
US7660912B2 (en) * 2006-10-18 2010-02-09 International Business Machines Corporation I/O adapter LPAR isolation in a hypertransport environment
JP4766498B2 (ja) 2008-12-24 2011-09-07 株式会社ソニー・コンピュータエンタテインメント ユーザレベルｄｍａとメモリアクセス管理を提供する方法と装置
JP5228938B2 (ja) * 2009-01-21 2013-07-03 ソニー株式会社 アクセスキー生成装置および情報処理装置
US8239663B2 (en) * 2009-05-30 2012-08-07 Lsi Corporation System and method for maintaining the security of memory contents and computer architecture employing the same
US8682639B2 (en) * 2010-09-21 2014-03-25 Texas Instruments Incorporated Dedicated memory window for emulation address
JP5541275B2 (ja) * 2011-12-28 2014-07-09 富士通株式会社 情報処理装置および不正アクセス防止方法
JP5703505B2 (ja) * 2012-10-15 2015-04-22 国立大学法人名古屋大学 バスパーティション構造を備えるコンピュータ
CN105120083B (zh) * 2012-12-31 2018-09-18 青岛海信移动通信技术股份有限公司 输入设备在输入处理实例中注册的控制方法及装置
US8924608B2 (en) 2013-06-25 2014-12-30 Airwatch Llc Peripheral device management
US9535857B2 (en) * 2013-06-25 2017-01-03 Airwatch Llc Autonomous device interaction
US9767044B2 (en) * 2013-09-24 2017-09-19 Intel Corporation Secure memory repartitioning
US9501222B2 (en) * 2014-05-09 2016-11-22 Micron Technology, Inc. Protection zones in virtualized physical addresses for reconfigurable memory systems using a memory abstraction
US9720868B2 (en) 2014-07-07 2017-08-01 Xilinx, Inc. Bridging inter-bus communications
JP6125734B2 (ja) 2014-12-26 2017-05-10 オリンパス株式会社 内視鏡システム
JP6406027B2 (ja) * 2015-01-20 2018-10-17 富士通株式会社 情報処理システム、情報処理装置、メモリアクセス制御方法
US10025727B2 (en) 2016-02-05 2018-07-17 Honeywell International Inc. Relay mechanism to facilitate processor communication with inaccessible input/output (I/O) device
US10324858B2 (en) * 2017-06-12 2019-06-18 Arm Limited Access control
US11609845B2 (en) * 2019-05-28 2023-03-21 Oracle International Corporation Configurable memory device connected to a microprocessor
US11086806B2 (en) * 2019-06-03 2021-08-10 Smart IOPS, Inc. Memory access system to access abstracted memory
JP7363344B2 (ja) * 2019-10-15 2023-10-18 オムロン株式会社 メモリ制御装置、および制御方法
US11782610B2 (en) * 2020-01-30 2023-10-10 Seagate Technology Llc Write and compare only data storage

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189384A (en) 1981-05-14 1982-11-20 Toshiba Corp Information processor
JPS62115554A (ja) 1985-11-15 1987-05-27 Fujitsu Ltd マルチプロセツサシステムにおける記憶保護方式
JPH04130553A (ja) 1990-09-20 1992-05-01 Matsushita Electric Ind Co Ltd 電子計算機
JP3124778B2 (ja) 1991-02-05 2001-01-15 株式会社日立製作所 アドレス変換装置
US5890220A (en) 1991-02-05 1999-03-30 Hitachi, Ltd. Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index buffers
DE4402903A1 (de) 1994-02-02 1995-08-03 Deutsche Telekom Mobil Verfahren zur paketweisen Datenübertragung in einem Mobilfunknetz
JP3264319B2 (ja) * 1997-06-30 2002-03-11 日本電気株式会社 バスブリッジ
US6839777B1 (en) 2000-09-11 2005-01-04 National Instruments Corporation System and method for transferring data over a communication medium using data transfer links
US6578122B2 (en) * 2001-03-01 2003-06-10 International Business Machines Corporation Using an access key to protect and point to regions in windows for infiniband
US6526491B2 (en) * 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US6775750B2 (en) * 2001-06-29 2004-08-10 Texas Instruments Incorporated System protection map
JP4130553B2 (ja) 2002-05-20 2008-08-06 日立工機株式会社 汎用充電装置及び汎用充電装置の充電法
JP2005242598A (ja) 2004-02-26 2005-09-08 Sony Corp 情報処理システム及び情報処理方法、並びにコンピュータ・プログラム
US7451249B2 (en) * 2005-03-21 2008-11-11 Hewlett-Packard Development Company, L.P. Method and apparatus for direct input and output in a virtual machine environment containing a guest operating system

Also Published As

Publication number Publication date
EP1903443A4 (de) 2009-03-04
WO2007129482A1 (ja) 2007-11-15
JPWO2007129482A1 (ja) 2009-09-17
US8006000B2 (en) 2011-08-23
US20090216921A1 (en) 2009-08-27
CN101326501A (zh) 2008-12-17
EP1903443A1 (de) 2008-03-26
CN101326501B (zh) 2010-12-15
EP1903443B1 (de) 2011-07-13
JP4219964B2 (ja) 2009-02-04

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