ATE516694T1 - Leiterplatte mit integrierten elektronischen komponenten und herstellungsverfahren dafür - Google Patents

Leiterplatte mit integrierten elektronischen komponenten und herstellungsverfahren dafür

Info

Publication number
ATE516694T1
ATE516694T1 AT08013360T AT08013360T ATE516694T1 AT E516694 T1 ATE516694 T1 AT E516694T1 AT 08013360 T AT08013360 T AT 08013360T AT 08013360 T AT08013360 T AT 08013360T AT E516694 T1 ATE516694 T1 AT E516694T1
Authority
AT
Austria
Prior art keywords
electronic components
circuit board
production method
integrated electronic
chip
Prior art date
Application number
AT08013360T
Other languages
English (en)
Inventor
Yoshikazu Kanemaru
Hiroshige Ohkawa
Kenichi Kawabata
Original Assignee
Tdk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corp filed Critical Tdk Corp
Application granted granted Critical
Publication of ATE516694T1 publication Critical patent/ATE516694T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10204—Dummy component, dummy PCB or template, e.g. for monitoring, controlling of processes, comparing, scanning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
AT08013360T 2007-07-25 2008-07-24 Leiterplatte mit integrierten elektronischen komponenten und herstellungsverfahren dafür ATE516694T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007193838A JP4518114B2 (ja) 2007-07-25 2007-07-25 電子部品内蔵基板及びその製造方法

Publications (1)

Publication Number Publication Date
ATE516694T1 true ATE516694T1 (de) 2011-07-15

Family

ID=40019399

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08013360T ATE516694T1 (de) 2007-07-25 2008-07-24 Leiterplatte mit integrierten elektronischen komponenten und herstellungsverfahren dafür

Country Status (5)

Country Link
US (1) US20090025961A1 (de)
EP (1) EP2019574B1 (de)
JP (1) JP4518114B2 (de)
CN (1) CN101355857B (de)
AT (1) ATE516694T1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8921705B2 (en) * 2008-11-28 2014-12-30 Ibiden Co., Ltd. Wiring board and fabrication method therefor
WO2012042668A1 (ja) * 2010-10-01 2012-04-05 株式会社メイコー 部品内蔵基板及び部品内蔵基板の製造方法
JP2013098410A (ja) * 2011-11-02 2013-05-20 Ibiden Co Ltd 多数個取り基板
CN104380848B (zh) * 2012-07-05 2019-07-23 株式会社村田制作所 部件内置基板
WO2014054387A1 (ja) * 2012-10-03 2014-04-10 株式会社村田製作所 部品内蔵基板およびその製造方法
JP2014107433A (ja) * 2012-11-28 2014-06-09 Ibiden Co Ltd 多数個取り基板
CN105224536A (zh) * 2014-05-29 2016-01-06 国际商业机器公司 划分数据库的方法和装置
KR102368069B1 (ko) 2014-10-22 2022-02-25 삼성전자주식회사 반도체 패키지의 제조 방법
KR102207272B1 (ko) * 2015-01-07 2021-01-25 삼성전기주식회사 인쇄회로기판, 그 제조방법, 및 전자부품 모듈
CA3014910A1 (en) 2016-02-22 2017-08-31 The Charles Stark Draper Laboratory, Inc. Method of manufacturing an implantable neural electrode interface platform
WO2019155643A1 (ja) * 2018-02-12 2019-08-15 株式会社Ｆｕｊｉ 装着精度測定用チップおよび装着精度測定用キット
JP7235379B2 (ja) * 2019-06-19 2023-03-08 住友電工デバイス・イノベーション株式会社 電子デバイスの製造方法
US20240222471A1 (en) * 2022-12-28 2024-07-04 At & S Austria Technologie & Systemtechnik Ag Warpage Control of Component Carrier with Dummy Components

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770645B2 (ja) 1986-06-11 1995-07-31 日本電気株式会社 混成集積回路
US5844319A (en) * 1997-03-03 1998-12-01 Motorola Corporation Microelectronic assembly with collar surrounding integrated circuit component on a substrate
JP3921756B2 (ja) * 1997-10-06 2007-05-30 株式会社デンソー プリント基板およびその製造方法
US6806428B1 (en) * 1999-04-16 2004-10-19 Matsushita Electric Industrial Co., Ltd. Module component and method of manufacturing the same
EP1227711B9 (de) * 1999-09-27 2008-08-13 Matsushita Electric Industrial Co., Ltd. Bauteilbestuckungsverfahren und -einrichtung
JP2001284783A (ja) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd 表面実装用基板及び表面実装構造
JP2002016173A (ja) * 2000-06-30 2002-01-18 Mitsubishi Electric Corp 半導体装置
JP2002324973A (ja) * 2001-04-26 2002-11-08 Sumitomo Metal Electronics Devices Inc セラミック多層基板
JP3816380B2 (ja) * 2001-12-14 2006-08-30 富士通株式会社 吸熱用ダミー部品を備えた基板ユニット及びその製造方法
JP4026705B2 (ja) * 2002-05-27 2007-12-26 Ｔｄｋ株式会社 積層型電子部品を構成する層及び積層型電子部品の製造方法
JP2004071698A (ja) * 2002-08-02 2004-03-04 Hitachi Metals Ltd 半導体パッケージ
JP3951854B2 (ja) * 2002-08-09 2007-08-01 カシオ計算機株式会社 半導体装置およびその製造方法
JP4194408B2 (ja) * 2003-04-03 2008-12-10 日本特殊陶業株式会社 補強材付き基板、半導体素子と補強材と基板とからなる配線基板
JP2005251792A (ja) * 2004-03-01 2005-09-15 Fujitsu Ltd 配線基板およびその製造方法
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
JP4526983B2 (ja) * 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
US8829661B2 (en) * 2006-03-10 2014-09-09 Freescale Semiconductor, Inc. Warp compensated package and method

Also Published As

Publication number Publication date
US20090025961A1 (en) 2009-01-29
EP2019574A2 (de) 2009-01-28
JP2009032824A (ja) 2009-02-12
EP2019574A3 (de) 2009-07-08
CN101355857A (zh) 2009-01-28
JP4518114B2 (ja) 2010-08-04
EP2019574B1 (de) 2011-07-13
CN101355857B (zh) 2011-04-06

Similar Documents

Publication Publication Date Title
EP2019574A3 (de) Tafel mit elektronischen Komponenten und Herstellungsverfahren dafür
ATE544323T1 (de) Montagesubstrat und herstellungsverfahren dafür
TW200802775A (en) An embedded electronic device and method for manufacturing an embedded electronic device
EP2019571A3 (de) Leiterplatte mit eingebetteten elektronischen Komponent und Herstellungsverfahren dafür
TW200610017A (en) Wiring board, method of manufacturing the same, and semiconductor device
MY146044A (en) Prepreg, method for manufacturing prepreg, substrate, and semiconductor device
TW200802537A (en) Semiconductor device having symbol pattern utilized as identification sign and its manufacture method
TW200731898A (en) Circuit board structure and method for fabricating the same
MX2009010232A (es) Una tarjeta gradual y metodo para fabricar una tarjeta gradual.
TW200802772A (en) Semiconductor package having embedded passive elements and method for manufacturing the same
TW200740317A (en) Electronic substrate manufacturing method, semiconductor device manufacturing method, and electronic equipment manufacturing method
TW200644297A (en) Semiconductor apparatus and manufacturing method thereof
TW200726334A (en) Circuit board structure having capacitance array and embedded electronic component and method for fabricating the same
TW200742524A (en) Multilayer printed circuit board
FI20060447A7 (fi) Menetelmä elektronisilla komponenteilla upotetun piirilevyn valmistamiseksi
WO2009054098A1 (ja) 部品内蔵配線基板および部品内蔵配線基板の製造方法
FI20075593A7 (fi) Menetelmä valmistaa komponenttiin upotettu piirilevy
TW200634915A (en) Manufacturing method of semiconductor device, semiconductor device, circuit board, electro-optic device, and electronic apparatus
TW200642554A (en) Multilayer circuit board with embedded components and method of manufacture
TW200644202A (en) Method of manufacturing flexible circuit substrate
DE502004012242D1 (de) Anordnung in Druckkontaktierung mit einem Leistungshalbleitermodul
WO2007120587A3 (en) Method for mounting protective covers on image capture devices and devices manufactured thereby
ATE540561T1 (de) Leiterplatte und herstellungsverfahren dafür
TW200709774A (en) Printed circuit board with improved thermal dissipating structure and electronic device with the same
WO2012042667A9 (ja) 部品内蔵基板の製造方法及びこれを用いた部品内蔵基板

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties