ATE520079T1 - DATA PROCESSING SYSTEM, DATA PROCESSING METHOD AND APPARATUS - Google Patents

DATA PROCESSING SYSTEM, DATA PROCESSING METHOD AND APPARATUS

Info

Publication number
ATE520079T1
ATE520079T1 AT07736020T AT07736020T ATE520079T1 AT E520079 T1 ATE520079 T1 AT E520079T1 AT 07736020 T AT07736020 T AT 07736020T AT 07736020 T AT07736020 T AT 07736020T AT E520079 T1 ATE520079 T1 AT E520079T1
Authority
AT
Austria
Prior art keywords
data path
data
path
component
data processing
Prior art date
Application number
AT07736020T
Other languages
German (de)
Inventor
Florian Bogenberger
Joaquim Kruecken
Christopher Temple
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Application granted granted Critical
Publication of ATE520079T1 publication Critical patent/ATE520079T1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1479—Generic software techniques for error detection or fault masking
    • G06F11/1487—Generic software techniques for error detection or fault masking using N-version programming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)

Abstract

A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.
AT07736020T 2007-05-25 2007-05-25 DATA PROCESSING SYSTEM, DATA PROCESSING METHOD AND APPARATUS ATE520079T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2007/051984 WO2008146091A1 (en) 2007-05-25 2007-05-25 Data processing system, data processing method, and apparatus

Publications (1)

Publication Number Publication Date
ATE520079T1 true ATE520079T1 (en) 2011-08-15

Family

ID=39273560

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07736020T ATE520079T1 (en) 2007-05-25 2007-05-25 DATA PROCESSING SYSTEM, DATA PROCESSING METHOD AND APPARATUS

Country Status (4)

Country Link
US (1) US8527681B2 (en)
EP (1) EP2153328B1 (en)
AT (1) ATE520079T1 (en)
WO (1) WO2008146091A1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8527681B2 (en) * 2007-05-25 2013-09-03 Freescale Semiconductor, Inc. Data processing system, data processing method, and apparatus
US8373435B2 (en) * 2008-09-30 2013-02-12 Freescale Semiconductor, Inc. Method and apparatus for handling an output mismatch
WO2011101707A1 (en) * 2010-02-16 2011-08-25 Freescale Semiconductor, Inc. Data processing method, data processor and apparatus including a data processor
US8683264B2 (en) * 2010-04-13 2014-03-25 International Business Machines Corporation Processing execution requests within different computing environments
JP5684514B2 (en) * 2010-08-19 2015-03-11 株式会社東芝 Redundant control system and calculation data transmission method thereof
DE102011086530A1 (en) * 2010-11-19 2012-05-24 Continental Teves Ag & Co. Ohg Microprocessor system with fault-tolerant architecture
US10142124B2 (en) 2012-05-24 2018-11-27 Infineon Technologies Ag System and method to transmit data over a bus system
US9842014B2 (en) 2012-11-22 2017-12-12 Nxp Usa, Inc. Data processing device, method of execution error detection and integrated circuit
DE102014217321A1 (en) * 2014-08-29 2016-03-03 Continental Teves Ag & Co. Ohg Microcontroller system and method for safety-critical motor vehicle systems and their use
US9823983B2 (en) 2014-09-25 2017-11-21 Nxp Usa, Inc. Electronic fault detection unit
DE102016215345A1 (en) 2016-08-17 2018-02-22 Siemens Aktiengesellschaft Method and device for redundant data processing
JP6848340B2 (en) * 2016-10-25 2021-03-24 株式会社リコー Information processing system, update method, information processing device and program
WO2018128204A1 (en) * 2017-01-06 2018-07-12 주식회사 알티스트 Multicore system capable of using lsm and dpm simultaneously by using partitioning technique
US10831578B2 (en) 2018-09-28 2020-11-10 Nxp Usa, Inc. Fault detection circuit with progress register and status register
US11132268B2 (en) * 2019-10-21 2021-09-28 The Boeing Company System and method for synchronizing communications between a plurality of processors
US12135970B2 (en) 2023-03-17 2024-11-05 The Boeing Company System and method for synchronizing processing between a plurality of processors
US12174703B2 (en) * 2023-03-17 2024-12-24 Dell Products L.P. System and method for managing recovery of management controllers

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3234637A1 (en) 1982-09-18 1984-03-22 Alfred Teves Gmbh, 6000 Frankfurt METHOD AND CIRCUIT FOR CONTROLLING A BRAKE-SLIP CONTROL SYSTEM
US5458404A (en) 1991-11-12 1995-10-17 Itt Automotive Europe Gmbh Redundant wheel sensor signal processing in both controller and monitoring circuits
US5812757A (en) 1993-10-08 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Processing board, a computer, and a fault recovery method for the computer
DE4341082A1 (en) 1993-12-02 1995-06-08 Teves Gmbh Alfred Circuit arrangement for safety-critical control systems
DE19529434B4 (en) 1995-08-10 2009-09-17 Continental Teves Ag & Co. Ohg Microprocessor system for safety-critical regulations
US5802265A (en) * 1995-12-01 1998-09-01 Stratus Computer, Inc. Transparent fault tolerant computer system
DE19631309A1 (en) 1996-08-02 1998-02-05 Teves Gmbh Alfred Microprocessor arrangement for a vehicle control system
DE19716197A1 (en) 1997-04-18 1998-10-22 Itt Mfg Enterprises Inc Microprocessor system for safety-critical regulations
DE19720618A1 (en) 1997-05-16 1998-11-19 Itt Mfg Enterprises Inc Microprocessor system for automotive control systems
US5835363A (en) * 1997-11-13 1998-11-10 Acer Peripherals, Inc. Power supply device featuring synchronous mode and asynchronous mode operation
DE19800311A1 (en) 1998-01-07 1999-07-08 Itt Mfg Enterprises Inc Electronic, digital device
US6327175B1 (en) * 1999-09-13 2001-12-04 Cypress Semiconductor Corporation Method and apparatus for controlling a memory array with a programmable register
US6615366B1 (en) 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
JP2002009864A (en) * 2000-06-20 2002-01-11 Sony Corp Control method and communication device
US6865179B1 (en) * 2000-07-20 2005-03-08 Lucent Technologies Inc. Apparatus and method for synchronous and asynchronous transfer mode switching of ATM traffic
US20020112070A1 (en) * 2000-12-08 2002-08-15 The Boeing Company Network controller for digitally controlling remote devices via a common bus
JP3628265B2 (en) * 2001-02-21 2005-03-09 株式会社半導体理工学研究センター Multiprocessor system unit
DE10124027A1 (en) 2001-05-16 2002-11-21 Continental Teves Ag & Co Ohg Method for operation of a microprocessor system equipped for execution of safety critical functions and uncritical functions, e.g. for a motor vehicle, in which safety critical and uncritical operations can be distinguished
DE10349580A1 (en) 2003-10-24 2005-05-25 Robert Bosch Gmbh Method and device for operand processing in a processor unit
US7613853B2 (en) * 2003-10-24 2009-11-03 Stmicroelectronics Pvt. Ltd. Output buffer circuit capable of synchronous and asynchronous data buffering using sensing circuit, and method and system of same
DE10349581A1 (en) 2003-10-24 2005-05-25 Robert Bosch Gmbh Method and device for switching between at least two operating modes of a processor unit
US7864730B2 (en) * 2004-01-06 2011-01-04 Sk Telecom Co. Ltd. Method for controlling multi-mode multi-band mobile communication terminal for hand-over between asynchronous communication network and synchronous communication network and mobile communication system therefor
KR100557104B1 (en) * 2004-01-14 2006-03-03 삼성전자주식회사 Dual mode mobile communication terminal for displaying visual information and method thereof
US7392426B2 (en) * 2004-06-15 2008-06-24 Honeywell International Inc. Redundant processing architecture for single fault tolerance
US7245552B2 (en) * 2005-06-22 2007-07-17 Infineon Technologies Ag Parallel data path architecture
DE102005037247A1 (en) 2005-08-08 2007-02-15 Robert Bosch Gmbh Method and device for controlling a memory access in a computer system having at least two execution units
EP1913478B1 (en) * 2005-08-11 2018-10-10 Continental Teves AG & Co. OHG Microprocessor system for controlling and/or regulating at least partly security-critical processes
KR100656455B1 (en) * 2005-12-27 2006-12-11 주식회사 하이닉스반도체 Device and method for controlling active cycle of semiconductor memory
KR100695289B1 (en) * 2006-03-09 2007-03-16 주식회사 하이닉스반도체 Address buffer and address buffering method of semiconductor memory device
US7501968B2 (en) * 2006-12-15 2009-03-10 Honeywell International, Inc. Integrated multi-mode sensor
US8527681B2 (en) * 2007-05-25 2013-09-03 Freescale Semiconductor, Inc. Data processing system, data processing method, and apparatus
US8010846B1 (en) * 2008-04-30 2011-08-30 Honeywell International Inc. Scalable self-checking processing platform including processors executing both coupled and uncoupled applications within a frame
IT1391785B1 (en) * 2008-11-21 2012-01-27 St Microelectronics Srl ELECTRONIC SYSTEM FOR DETECTION OF FAILURE

Also Published As

Publication number Publication date
WO2008146091A1 (en) 2008-12-04
EP2153328A1 (en) 2010-02-17
US8527681B2 (en) 2013-09-03
EP2153328B1 (en) 2011-08-10
US20110066779A1 (en) 2011-03-17

Similar Documents

Publication Publication Date Title
TW200943070A (en) Memory device with network on chip methods, apparatus, and systems
WO2007149495A3 (en) Program binding system, method and software for a resilient integrated circuit architecture
ATE495499T1 (en) 12C BUS INTERFACE WITH PARALLEL OPERATION MODE
WO2016198961A3 (en) System and method for network tapestry multiprotocol integration
WO2008025017A3 (en) Configurable personal audiovisual device for use in networked application-sharing system
TW200740296A (en) A lighting system and a method for controlling a lighting system
NO20075529L (en) credential Interface
WO2008146517A1 (en) Optical network unit and optical transmission system
WO2013128007A3 (en) Network infrastructure component, composite system having a plurality of network infrastructure components, and use of the composite system
WO2007120804A3 (en) Multiplexing a parallel bus interface and a flash memory interface
WO2008086140A3 (en) Behavioral modification system and method
WO2009007378A3 (en) Apparatus for automation of the operative functionalities of one or more loads of an environment
WO2010025205A3 (en) Method and apparatus to combine power and control signals in a mobile computing device
TW200729847A (en) Extended address space capability for an industrial protocol
TW200729748A (en) Multimode communication device with shared signal path programmable filter
PL1869836T3 (en) Master unit communication system and method for operation thereof
WO2008004185A3 (en) Electronic device, system on chip and method for monitoring data traffic
WO2007084489A3 (en) Cooling system and method
WO2008004187A3 (en) Electronic device, system on chip and method of monitoring data traffic
DE502005011042D1 (en) FUEL CELL SYSTEM
DE502007006334D1 (en) Redundant communication network
MX2025006676A (en) Interface, electronic device, and communication system
ATE551884T1 (en) ELECTRONIC APPARATUS AND METHOD FOR INSPECTING A CIRCUIT BOARD
NO20083721L (en) High speed redundant data processing system
TW200643731A (en) Systems and methods for facilitating wireless communication between various components of a distributed system

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties