BRPI0917905A8 - Dispositivo de memória - Google Patents

Dispositivo de memória

Info

Publication number
BRPI0917905A8
BRPI0917905A8 BRPI0917905A BRPI0917905A BRPI0917905A8 BR PI0917905 A8 BRPI0917905 A8 BR PI0917905A8 BR PI0917905 A BRPI0917905 A BR PI0917905A BR PI0917905 A BRPI0917905 A BR PI0917905A BR PI0917905 A8 BRPI0917905 A8 BR PI0917905A8
Authority
BR
Brazil
Prior art keywords
effect transistor
type field
memory
memory device
additionally
Prior art date
Application number
BRPI0917905A
Other languages
English (en)
Inventor
A De La Cruz Louis
I Remington Scott
Original Assignee
Freescale Semiconductor Inc
Nxp Usa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Nxp Usa Inc filed Critical Freescale Semiconductor Inc
Publication of BRPI0917905A2 publication Critical patent/BRPI0917905A2/pt
Publication of BRPI0917905A8 publication Critical patent/BRPI0917905A8/pt
Publication of BRPI0917905B1 publication Critical patent/BRPI0917905B1/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

DISPOSITIVO DE MEMÓRIA E MÉTODO DO MESMO O presente pedido revela uma matriz de memória onde cada célula de bit de memória (MC) da matriz inclui um nivelador (112). Adicionalmente, cada célula de bit de memória inclui uma porta de gravação (120) que inclui portas de passagem que podem incluir um transistor de efeito de campo tipo-p (125, 126) e um transistor de efeito de campo tipo-n (121, 123). Os eletrodos de controle do transistor de efeito de campo tipo-p e do transistor de efeito de campo tipo-n são conectados juntos como parte de um nó comum (WLB). Adicionalmente, um eletrodo de corrente do transistor de efeito de campo tipo-p e um eletrodo de corrente do transistor de efeito de campo tipo-n são conectados juntos para formar um nó comum (135, 136).
BRPI0917905-4A 2008-08-27 2009-06-25 dispositivo de memória BRPI0917905B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/199,093 2008-08-27
US12/199,093 US7859919B2 (en) 2008-08-27 2008-08-27 Memory device and method thereof
PCT/US2009/048656 WO2010027547A1 (en) 2008-08-27 2009-06-25 Memory device and method thereof

Publications (3)

Publication Number Publication Date
BRPI0917905A2 BRPI0917905A2 (pt) 2015-11-10
BRPI0917905A8 true BRPI0917905A8 (pt) 2017-10-10
BRPI0917905B1 BRPI0917905B1 (pt) 2020-11-10

Family

ID=41725264

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0917905-4A BRPI0917905B1 (pt) 2008-08-27 2009-06-25 dispositivo de memória

Country Status (5)

Country Link
US (1) US7859919B2 (pt)
JP (1) JP5382554B2 (pt)
CN (1) CN102132347B (pt)
BR (1) BRPI0917905B1 (pt)
WO (1) WO2010027547A1 (pt)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7961499B2 (en) * 2009-01-22 2011-06-14 Qualcomm Incorporated Low leakage high performance static random access memory cell using dual-technology transistors
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10860318B2 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10777262B1 (en) 2016-12-06 2020-09-15 Gsi Technology, Inc. Read data processing circuits and methods associated memory cells
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10700683B1 (en) * 2018-08-28 2020-06-30 Qualcomm Incorporated Dynamic power supply shifting
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
TWI762317B (zh) * 2021-05-17 2022-04-21 力晶積成電子製造股份有限公司 感測電路以及測試裝置

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2005601A (en) * 1934-11-17 1935-06-18 Ind Rayon Corp Pickling of ferrous metals
JPS5968889A (ja) 1982-10-08 1984-04-18 Toshiba Corp 半導体記憶装置
JP3204848B2 (ja) 1994-08-09 2001-09-04 株式会社東芝 レベル変換回路及びこのレベル変換回路を用いてレベル変換されたデータを出力する方法
US5546026A (en) 1995-03-01 1996-08-13 Cirrus Logic, Inc. Low-voltage high-performance dual-feedback dynamic sense amplifier
US5696721A (en) 1995-05-05 1997-12-09 Texas Instruments Incorporated Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range
KR0145851B1 (ko) 1995-06-30 1998-11-02 김광호 반도체 메모리 장치의 전압 변환회로
TW435007B (en) 1996-04-08 2001-05-16 Hitachi Ltd Semiconductor integrated circuit device
US6122191A (en) 1996-05-01 2000-09-19 Cypress Semiconductor Corporation Semiconductor non-volatile device including embedded non-volatile elements
JPH117775A (ja) * 1997-06-17 1999-01-12 Sony Corp 半導体記憶装置
US5973955A (en) 1998-02-02 1999-10-26 Motorola, Inc. Comparison circuit utilizing a differential amplifier
US6040991A (en) 1999-01-04 2000-03-21 International Business Machines Corporation SRAM memory cell having reduced surface area
GB2347567A (en) 1999-03-05 2000-09-06 Sharp Kk CMOS level shifters and sense amplifiers
JP4748877B2 (ja) * 2000-07-10 2011-08-17 ルネサスエレクトロニクス株式会社 記憶装置
JP2002197881A (ja) * 2000-12-27 2002-07-12 Toshiba Corp レベルシフタ及びレベルシフタを備えた半導体記憶装置
US6621758B2 (en) 2001-05-04 2003-09-16 Texas Instruments Incorporated Method for providing a low power read only memory banking methodology with efficient bus muxing
DE10126312B4 (de) 2001-05-30 2015-10-22 Infineon Technologies Ag Halbleiterspeicher mit einem Signalpfad
US6834024B2 (en) 2001-10-23 2004-12-21 Ip-First, Llc Reduced size multi-port register cell
US6639827B2 (en) 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6654277B1 (en) 2002-05-14 2003-11-25 International Business Machines Corp. SRAM with improved noise sensitivity
US20030214867A1 (en) 2002-05-17 2003-11-20 Matthew Goldman Serially sensing the output of multilevel cell arrays
US7173875B2 (en) 2002-11-29 2007-02-06 International Business Machines Corporation SRAM array with improved cell stability
US6774696B2 (en) 2002-12-12 2004-08-10 Intel Corporation Level shifter and voltage translator
US6741111B1 (en) 2003-04-21 2004-05-25 Pericom Semiconductor Corp. Data register for buffering double-data-rate DRAMs with reduced data-input-path power consumption
KR100505710B1 (ko) 2003-09-15 2005-08-02 삼성전자주식회사 임베디드 메모리 장치의 저전력 소비형 데이터 입출력회로 및 이에 대한 데이터 입출력 방법
US7088630B2 (en) 2004-04-23 2006-08-08 Macronix International Co., Ltd. Circuit and method for high speed sensing
JP2006196061A (ja) * 2005-01-12 2006-07-27 Toshiba Corp 電圧切換回路、及びこれを用いた半導体記憶装置
US7161827B2 (en) 2005-01-12 2007-01-09 Freescale Semiconductor, Inc. SRAM having improved cell stability and method therefor
US20060152255A1 (en) 2005-01-13 2006-07-13 Elite Semiconductor Memory Technology Inc. Gate oxide protected I/O circuit
US7355905B2 (en) 2005-07-01 2008-04-08 P.A. Semi, Inc. Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
US7167392B1 (en) 2005-07-15 2007-01-23 National Semiconductor Corporation Non-volatile memory cell with improved programming technique
US7239558B1 (en) 2005-09-26 2007-07-03 National Semiconductor Corporation Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle
EP1835507B1 (en) 2006-03-17 2010-08-18 STMicroelectronics Srl Level shifter for semiconductor memory device implemented with low-voltage transistors
US7292495B1 (en) 2006-06-29 2007-11-06 Freescale Semiconductor, Inc. Integrated circuit having a memory with low voltage read/write operation
JP5282430B2 (ja) * 2008-03-27 2013-09-04 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JP5382554B2 (ja) 2014-01-08
BRPI0917905B1 (pt) 2020-11-10
WO2010027547A1 (en) 2010-03-11
US20100054051A1 (en) 2010-03-04
BRPI0917905A2 (pt) 2015-11-10
CN102132347A (zh) 2011-07-20
US7859919B2 (en) 2010-12-28
CN102132347B (zh) 2014-05-28
JP2012501512A (ja) 2012-01-19

Similar Documents

Publication Publication Date Title
BRPI0917905A8 (pt) Dispositivo de memória
TW201612911A (en) Memory device
JP2012257201A5 (pt)
JP2013008435A5 (pt)
JP2011187940A5 (pt)
ATE534994T1 (de) Sram-reststromreduktionsschaltung
IN2014CN04993A (pt)
SG10201806114YA (en) Semiconductor memory devices
WO2012125580A3 (en) Non-volatile anti-fuse memory cell
EP3971988A3 (en) Virtual ground non-volatile memory array
WO2012170409A3 (en) Techniques for providing a semiconductor memory device
WO2016137681A3 (en) P-type field-effect transistor (pfet)-based sense amplifiers for reading pfet pass-gate memory bit cells, and related memory systems and methods
ATE523882T1 (de) Sram-speicherzelle auf basis von doppelgate- transistoren mit mittel zur erweiterung eines schreibbereichs
JP2011249782A5 (pt)
WO2011140044A3 (en) Techniques for refreshing a semiconductor memory device
JP2013016247A5 (pt)
JP2012064930A5 (ja) 半導体メモリ装置
BR112018067658A2 (pt) sistema e método para reduzir o esforço de tensão de programação em dispositivos de célula de memória
WO2011096978A3 (en) 5-transistor non-volatile memory cell
JP2015008030A5 (pt)
JP2012238372A5 (pt)
JP2016105343A5 (pt)
WO2007078885A3 (en) Multi-level memory cell sensing
WO2013062611A3 (en) Common doped region with separate gate control for a non-volatile memory cell
JP2016219089A5 (ja) 半導体装置

Legal Events

Date Code Title Description
B25A Requested transfer of rights approved

Owner name: NXP USA, INC. (US)

B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06T Formal requirements before examination [chapter 6.20 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: AS CLASSIFICACOES ANTERIORES ERAM: G11C 7/10 , G11C 5/14

Ipc: G11C 11/412 (1990.01)

B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B06A Patent application procedure suspended [chapter 6.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 10/11/2020, OBSERVADAS AS CONDICOES LEGAIS.