ATE526633T1 - Speicherbusabschluss - Google Patents

Speicherbusabschluss

Info

Publication number
ATE526633T1
ATE526633T1 AT03739204T AT03739204T ATE526633T1 AT E526633 T1 ATE526633 T1 AT E526633T1 AT 03739204 T AT03739204 T AT 03739204T AT 03739204 T AT03739204 T AT 03739204T AT E526633 T1 ATE526633 T1 AT E526633T1
Authority
AT
Austria
Prior art keywords
storage bus
bus termination
bus line
memory bus
memory
Prior art date
Application number
AT03739204T
Other languages
English (en)
Inventor
John Zumkehr
James Chandler
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE526633T1 publication Critical patent/ATE526633T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Memory System (AREA)
AT03739204T 2002-06-21 2003-06-19 Speicherbusabschluss ATE526633T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/177,047 US6965529B2 (en) 2002-06-21 2002-06-21 Memory bus termination
PCT/US2003/019307 WO2004001616A1 (en) 2002-06-21 2003-06-19 Memory bus termination

Publications (1)

Publication Number Publication Date
ATE526633T1 true ATE526633T1 (de) 2011-10-15

Family

ID=29734273

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03739204T ATE526633T1 (de) 2002-06-21 2003-06-19 Speicherbusabschluss

Country Status (9)

Country Link
US (1) US6965529B2 (de)
EP (1) EP1516260B1 (de)
JP (1) JP2006509270A (de)
KR (1) KR100680690B1 (de)
CN (1) CN100583075C (de)
AT (1) ATE526633T1 (de)
AU (1) AU2003245576A1 (de)
TW (1) TWI242717B (de)
WO (1) WO2004001616A1 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657906B2 (en) * 2001-11-28 2003-12-02 Micron Technology, Inc. Active termination circuit and method for controlling the impedance of external integrated circuit terminals
US20040017374A1 (en) * 2002-07-25 2004-01-29 Chi-Yang Lin Imaging data accessing method
US6842035B2 (en) * 2002-12-31 2005-01-11 Intel Corporation Apparatus and method for bus signal termination compensation during detected quiet cycle
US6924660B2 (en) * 2003-09-08 2005-08-02 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7095245B2 (en) * 2003-11-14 2006-08-22 Intel Corporation Internal voltage reference for memory interface
US7019553B2 (en) * 2003-12-01 2006-03-28 Micron Technology, Inc. Method and circuit for off chip driver control, and memory device using same
US6980020B2 (en) * 2003-12-19 2005-12-27 Rambus Inc. Calibration methods and circuits for optimized on-die termination
US7196567B2 (en) * 2004-12-20 2007-03-27 Rambus Inc. Systems and methods for controlling termination resistance values for a plurality of communication channels
JP4159553B2 (ja) * 2005-01-19 2008-10-01 エルピーダメモリ株式会社 半導体装置の出力回路及びこれを備える半導体装置、並びに、出力回路の特性調整方法
US7215579B2 (en) * 2005-02-18 2007-05-08 Micron Technology, Inc. System and method for mode register control of data bus operating mode and impedance
US7590392B2 (en) * 2005-10-31 2009-09-15 Intel Corporation Transmitter compensation
US7439760B2 (en) 2005-12-19 2008-10-21 Rambus Inc. Configurable on-die termination
US7479799B2 (en) * 2006-03-14 2009-01-20 Inphi Corporation Output buffer with switchable output impedance
US7486104B2 (en) 2006-06-02 2009-02-03 Rambus Inc. Integrated circuit with graduated on-die termination
US8165025B2 (en) * 2006-12-08 2012-04-24 Ixia Method and apparatus for generating a unique packet identifier
US8599631B2 (en) 2006-12-21 2013-12-03 Rambus Inc. On-die termination of address and command signals
US20080162801A1 (en) * 2006-12-29 2008-07-03 Ripan Das Series termination for a low power memory interface
US20090080266A1 (en) * 2007-09-25 2009-03-26 Zumkehr John F Double data rate (ddr) low power idle mode through reference offset
US8239629B2 (en) * 2009-03-31 2012-08-07 Micron Technology, Inc. Hierarchical memory architecture to connect mass storage devices
JP5570619B2 (ja) * 2010-02-23 2014-08-13 ラムバス・インコーポレーテッド 異なるメモリ種類にアクセスする異なる速度での時分割多重化
WO2011159465A2 (en) 2010-06-17 2011-12-22 Rambus Inc. Balanced on-die termination
US8519737B2 (en) * 2011-07-01 2013-08-27 Apple Inc. Controller interface providing improved signal integrity
US8713404B2 (en) 2011-07-01 2014-04-29 Apple Inc. Controller interface providing improved data reliability
KR102089613B1 (ko) 2013-01-02 2020-03-16 삼성전자주식회사 불 휘발성 메모리 장치 및 그것을 포함한 메모리 시스템
US9843436B2 (en) * 2015-06-27 2017-12-12 Intel Corporation Flexible interconnect architecture
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
US9766831B2 (en) 2015-10-14 2017-09-19 Micron Technology, Inc. Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
US10348270B2 (en) 2016-12-09 2019-07-09 Micron Technology, Inc. Apparatuses and methods for calibrating adjustable impedances of a semiconductor device
US9767921B1 (en) 2016-12-30 2017-09-19 Micron Technology, Inc. Timing based arbiter systems and circuits for ZQ calibration
US10193711B2 (en) 2017-06-22 2019-01-29 Micron Technology, Inc. Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device
US10615798B2 (en) 2017-10-30 2020-04-07 Micron Technology, Inc. Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
TWI645414B (zh) * 2017-11-07 2018-12-21 瑞昱半導體股份有限公司 記憶體控制器
CN109785872B (zh) * 2017-11-10 2020-10-09 瑞昱半导体股份有限公司 记忆体控制器
US10205451B1 (en) 2018-01-29 2019-02-12 Micron Technology, Inc. Methods and apparatuses for dynamic step size for impedance calibration of a semiconductor device
US10917093B1 (en) * 2019-11-05 2021-02-09 Micron Technology, Inc. Self-adaptive termination impedance circuit
US10747245B1 (en) 2019-11-19 2020-08-18 Micron Technology, Inc. Apparatuses and methods for ZQ calibration
EP4390925A4 (de) * 2021-11-04 2025-01-01 Samsung Electronics Co., Ltd. Elektronische vorrichtung zur steuerung des betriebs eines flüchtigen speichers und betriebsverfahren dafür

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5919252A (en) 1991-07-29 1999-07-06 Micron Electronics, Inc. Process and apparatus for adaptive bus termination
US5784291A (en) * 1994-12-22 1998-07-21 Texas Instruments, Incorporated CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
JPH1020974A (ja) 1996-07-03 1998-01-23 Fujitsu Ltd バス構造及び入出力バッファ
JP3743789B2 (ja) * 1996-10-24 2006-02-08 株式会社ルネサステクノロジ メモリとプロセサとが同一チップ上に形成されたマイクロコンピュータ
US6051989A (en) 1997-05-30 2000-04-18 Lucent Technologies Inc. Active termination of a conductor for bi-directional signal transmission
US6347850B1 (en) 1999-12-23 2002-02-19 Intel Corporation Programmable buffer circuit
US6256235B1 (en) * 2000-06-23 2001-07-03 Micron Technology, Inc. Adjustable driver pre-equalization for memory subsystems
US6316980B1 (en) 2000-06-30 2001-11-13 Intel Corporation Calibrating data strobe signal using adjustable delays with feedback
US6559690B2 (en) * 2001-03-15 2003-05-06 Micron Technology, Inc. Programmable dual drive strength output buffer with a shared boot circuit

Also Published As

Publication number Publication date
CN100583075C (zh) 2010-01-20
US6965529B2 (en) 2005-11-15
TWI242717B (en) 2005-11-01
AU2003245576A1 (en) 2004-01-06
TW200413933A (en) 2004-08-01
US20030235084A1 (en) 2003-12-25
CN1662895A (zh) 2005-08-31
EP1516260B1 (de) 2011-09-28
WO2004001616A1 (en) 2003-12-31
JP2006509270A (ja) 2006-03-16
EP1516260A1 (de) 2005-03-23
HK1075717A1 (en) 2005-12-23
KR20050005561A (ko) 2005-01-13
KR100680690B1 (ko) 2007-02-09

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