ATE526682T1 - Integrationsprozessablauf für flash-bausteine mit niedrigem lückenfüll-seitenverhältnis - Google Patents

Integrationsprozessablauf für flash-bausteine mit niedrigem lückenfüll-seitenverhältnis

Info

Publication number
ATE526682T1
ATE526682T1 AT06825851T AT06825851T ATE526682T1 AT E526682 T1 ATE526682 T1 AT E526682T1 AT 06825851 T AT06825851 T AT 06825851T AT 06825851 T AT06825851 T AT 06825851T AT E526682 T1 ATE526682 T1 AT E526682T1
Authority
AT
Austria
Prior art keywords
aspect ratio
process flow
dielectric
integration process
gap fill
Prior art date
Application number
AT06825851T
Other languages
English (en)
Inventor
Tuan D Pham
Masaaki Higashitani
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corp filed Critical Sandisk Corp
Application granted granted Critical
Publication of ATE526682T1 publication Critical patent/ATE526682T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)
AT06825851T 2005-10-18 2006-10-10 Integrationsprozessablauf für flash-bausteine mit niedrigem lückenfüll-seitenverhältnis ATE526682T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/254,142 US7541240B2 (en) 2005-10-18 2005-10-18 Integration process flow for flash devices with low gap fill aspect ratio
PCT/US2006/039931 WO2007047390A2 (en) 2005-10-18 2006-10-10 Integration process flow for flash devices

Publications (1)

Publication Number Publication Date
ATE526682T1 true ATE526682T1 (de) 2011-10-15

Family

ID=37635752

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06825851T ATE526682T1 (de) 2005-10-18 2006-10-10 Integrationsprozessablauf für flash-bausteine mit niedrigem lückenfüll-seitenverhältnis

Country Status (8)

Country Link
US (1) US7541240B2 (de)
EP (2) EP2320455B1 (de)
JP (1) JP4950207B2 (de)
KR (1) KR101029696B1 (de)
CN (1) CN101288164B (de)
AT (1) ATE526682T1 (de)
TW (1) TWI384588B (de)
WO (1) WO2007047390A2 (de)

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JP4950207B2 (ja) 2012-06-13
EP2320455B1 (de) 2012-07-18
TWI384588B (zh) 2013-02-01
EP2320455A1 (de) 2011-05-11
CN101288164B (zh) 2011-03-30
JP2009512228A (ja) 2009-03-19
KR20080075086A (ko) 2008-08-14
US7541240B2 (en) 2009-06-02
WO2007047390A3 (en) 2007-06-14
WO2007047390A2 (en) 2007-04-26
EP1938371A2 (de) 2008-07-02
CN101288164A (zh) 2008-10-15
EP1938371B1 (de) 2011-09-28
US20070087504A1 (en) 2007-04-19
TW200731473A (en) 2007-08-16
KR101029696B1 (ko) 2011-04-18

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