ATE528889T1 - Elektronische vorrichtung und verfahren zur kommunikationsressourcenzuteilung - Google Patents

Elektronische vorrichtung und verfahren zur kommunikationsressourcenzuteilung

Info

Publication number
ATE528889T1
ATE528889T1 AT06744916T AT06744916T ATE528889T1 AT E528889 T1 ATE528889 T1 AT E528889T1 AT 06744916 T AT06744916 T AT 06744916T AT 06744916 T AT06744916 T AT 06744916T AT E528889 T1 ATE528889 T1 AT E528889T1
Authority
AT
Austria
Prior art keywords
slot
electronic device
interconnect means
processing modules
communication resources
Prior art date
Application number
AT06744916T
Other languages
English (en)
Inventor
Edwin Rijpkema
John Dielissen
Original Assignee
St Ericsson Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Ericsson Sa filed Critical St Ericsson Sa
Application granted granted Critical
Publication of ATE528889T1 publication Critical patent/ATE528889T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13098—Mobile subscriber
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1332—Logic circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Small-Scale Networks (AREA)
AT06744916T 2005-05-26 2006-05-11 Elektronische vorrichtung und verfahren zur kommunikationsressourcenzuteilung ATE528889T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05104512 2005-05-26
PCT/IB2006/051487 WO2006126127A2 (en) 2005-05-26 2006-05-11 Electronic device and method of communication resource allocation

Publications (1)

Publication Number Publication Date
ATE528889T1 true ATE528889T1 (de) 2011-10-15

Family

ID=37258890

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06744916T ATE528889T1 (de) 2005-05-26 2006-05-11 Elektronische vorrichtung und verfahren zur kommunikationsressourcenzuteilung

Country Status (6)

Country Link
US (1) US7809024B2 (de)
EP (1) EP1889412B1 (de)
JP (1) JP4756158B2 (de)
CN (1) CN101180841B (de)
AT (1) ATE528889T1 (de)
WO (1) WO2006126127A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9021156B2 (en) * 2011-08-31 2015-04-28 Prashanth Nimmala Integrating intellectual property (IP) blocks into a processor
US8930602B2 (en) 2011-08-31 2015-01-06 Intel Corporation Providing adaptive bandwidth allocation for a fixed priority arbiter
US8713234B2 (en) 2011-09-29 2014-04-29 Intel Corporation Supporting multiple channels of a single interface
US8711875B2 (en) 2011-09-29 2014-04-29 Intel Corporation Aggregating completion messages in a sideband interface
US8805926B2 (en) 2011-09-29 2014-08-12 Intel Corporation Common idle state, active state and credit management for an interface
US8874976B2 (en) 2011-09-29 2014-10-28 Intel Corporation Providing error handling support to legacy devices
US8713240B2 (en) 2011-09-29 2014-04-29 Intel Corporation Providing multiple decode options for a system-on-chip (SoC) fabric
US8775700B2 (en) 2011-09-29 2014-07-08 Intel Corporation Issuing requests to a fabric
US8929373B2 (en) 2011-09-29 2015-01-06 Intel Corporation Sending packets with expanded headers
US9053251B2 (en) 2011-11-29 2015-06-09 Intel Corporation Providing a sideband message interface for system on a chip (SoC)
US9571402B2 (en) * 2013-05-03 2017-02-14 Netspeed Systems Congestion control and QoS in NoC by regulating the injection traffic
CN107566074B (zh) 2016-06-30 2019-06-11 华为技术有限公司 光传送网中传送客户信号的方法及传送设备
US10666578B2 (en) * 2016-09-06 2020-05-26 Taiwan Semiconductor Manufacturing Company Limited Network-on-chip system and a method of generating the same
US10911261B2 (en) 2016-12-19 2021-02-02 Intel Corporation Method, apparatus and system for hierarchical network on chip routing
US10846126B2 (en) 2016-12-28 2020-11-24 Intel Corporation Method, apparatus and system for handling non-posted memory write transactions in a fabric
US11264361B2 (en) 2019-06-05 2022-03-01 Invensas Corporation Network on layer enabled architectures

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5875309A (en) * 1997-04-18 1999-02-23 3Com Corporation Arbitration system using linked table
JP3970467B2 (ja) * 1999-03-18 2007-09-05 富士通株式会社 無線通信システム
US6665495B1 (en) * 2000-10-27 2003-12-16 Yotta Networks, Inc. Non-blocking, scalable optical router architecture and method for routing optical traffic
EP1625757B1 (de) * 2003-05-14 2007-04-18 Koninklijke Philips Electronics N.V. Zeitmultiplexleitungsvermittlender router
KR101125647B1 (ko) * 2004-04-05 2012-03-27 코닌클리케 필립스 일렉트로닉스 엔.브이. 시간 슬롯 할당을 위한 집적 회로 및 방법, 및 데이터 처리 시스템
EP1605727A1 (de) * 2004-06-09 2005-12-14 Koninklijke Philips Electronics N.V. Integrierte Schaltungsanordnung und Verfahren zur Zuordnung von Zeitlagen
JP2008520119A (ja) * 2004-11-09 2008-06-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子デバイスおよび通信資源割り当て方法
JPWO2006085353A1 (ja) * 2005-02-08 2008-06-26 富士通株式会社 セルラー無線通信システムにおけるスロット割り当て方法及び同システムに用いられる基地局
JP2008535435A (ja) * 2005-04-06 2008-08-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ ネットワーク・オン・チップ環境及び遅延低減方法

Also Published As

Publication number Publication date
JP4756158B2 (ja) 2011-08-24
US7809024B2 (en) 2010-10-05
EP1889412A2 (de) 2008-02-20
WO2006126127A2 (en) 2006-11-30
EP1889412B1 (de) 2011-10-12
CN101180841B (zh) 2011-11-30
JP2008543151A (ja) 2008-11-27
CN101180841A (zh) 2008-05-14
US20080310458A1 (en) 2008-12-18
WO2006126127A3 (en) 2007-03-29

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Legal Events

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