ATE532215T1 - Halbleiterkapselung und deren herstellung - Google Patents

Halbleiterkapselung und deren herstellung

Info

Publication number
ATE532215T1
ATE532215T1 AT09706541T AT09706541T ATE532215T1 AT E532215 T1 ATE532215 T1 AT E532215T1 AT 09706541 T AT09706541 T AT 09706541T AT 09706541 T AT09706541 T AT 09706541T AT E532215 T1 ATE532215 T1 AT E532215T1
Authority
AT
Austria
Prior art keywords
base frame
bond pads
wiring
production
connecting structures
Prior art date
Application number
AT09706541T
Other languages
English (en)
Inventor
Paresh Limaye
Jan Vanfleteren
Eric Beyne
Original Assignee
Imec
Univ Leuven Kath
Univ Gent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Univ Leuven Kath, Univ Gent filed Critical Imec
Application granted granted Critical
Publication of ATE532215T1 publication Critical patent/ATE532215T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
AT09706541T 2008-02-01 2009-01-30 Halbleiterkapselung und deren herstellung ATE532215T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2566808P 2008-02-01 2008-02-01
PCT/EP2009/051089 WO2009095486A2 (en) 2008-02-01 2009-01-30 Semiconductor package

Publications (1)

Publication Number Publication Date
ATE532215T1 true ATE532215T1 (de) 2011-11-15

Family

ID=40786865

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09706541T ATE532215T1 (de) 2008-02-01 2009-01-30 Halbleiterkapselung und deren herstellung

Country Status (4)

Country Link
US (1) US8450825B2 (de)
EP (1) EP2243161B1 (de)
AT (1) ATE532215T1 (de)
WO (1) WO2009095486A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8952525B2 (en) * 2011-03-04 2015-02-10 Hitachi Automotive Systems, Ltd. Semiconductor module and method for manufacturing semiconductor module
US8664041B2 (en) * 2012-04-12 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for designing a package and substrate layout
US8756546B2 (en) * 2012-07-25 2014-06-17 International Business Machines Corporation Elastic modulus mapping of a chip carrier in a flip chip package
US9335034B2 (en) 2013-09-27 2016-05-10 Osram Sylvania Inc Flexible circuit board for electronic applications, light source containing same, and method of making
US9059054B1 (en) * 2014-01-09 2015-06-16 Nvidia Corporation Integrated circuit package having improved coplanarity
KR102198858B1 (ko) 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US9559026B2 (en) 2015-02-26 2017-01-31 Infineon Technologies Americas Corp. Semiconductor package having a multi-layered base
US9706662B2 (en) * 2015-06-30 2017-07-11 Raytheon Company Adaptive interposer and electronic apparatus
CN106298862A (zh) * 2016-10-31 2017-01-04 昆山工研院新型平板显示技术中心有限公司 显示模组
US11107753B2 (en) * 2018-11-28 2021-08-31 Semiconductor Components Industries, Llc Packaging structure for gallium nitride devices
CN120613340A (zh) * 2024-03-05 2025-09-09 华为技术有限公司 一种多芯片的封装结构、光模块和光通信系统

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0680873B2 (ja) * 1986-07-11 1994-10-12 株式会社東芝 回路基板
KR920007161A (ko) * 1990-09-26 1992-04-28 기따지마 요시도기 다층 리드프레임(lead frame), 이 다층 리드프레임에 사용되는 도전판 및 이 도전판의 제조방법
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455446A (en) * 1994-06-30 1995-10-03 Motorola, Inc. Leaded semiconductor package having temperature controlled lead length
US6486003B1 (en) * 1996-12-13 2002-11-26 Tessera, Inc. Expandable interposer for a microelectronic package and method therefor
US5804771A (en) * 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
US6299053B1 (en) 1998-08-19 2001-10-09 Kulicke & Soffa Holdings, Inc. Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch
TW563895U (en) * 2003-03-06 2003-11-21 Advanced Semiconductor Eng Thin type ball grid array package
JP2004288834A (ja) * 2003-03-20 2004-10-14 Fujitsu Ltd 電子部品の実装方法、実装構造及びパッケージ基板
US20070273023A1 (en) * 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body

Also Published As

Publication number Publication date
EP2243161A2 (de) 2010-10-27
WO2009095486A3 (en) 2009-10-01
US20110037179A1 (en) 2011-02-17
US8450825B2 (en) 2013-05-28
WO2009095486A2 (en) 2009-08-06
EP2243161B1 (de) 2011-11-02

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