ATE535013T1 - Verbindungsstruktur und herstellungsverfahren dafür - Google Patents

Verbindungsstruktur und herstellungsverfahren dafür

Info

Publication number
ATE535013T1
ATE535013T1 AT06740771T AT06740771T ATE535013T1 AT E535013 T1 ATE535013 T1 AT E535013T1 AT 06740771 T AT06740771 T AT 06740771T AT 06740771 T AT06740771 T AT 06740771T AT E535013 T1 ATE535013 T1 AT E535013T1
Authority
AT
Austria
Prior art keywords
electrical conductor
core electrical
electrically conductive
sides
physical contact
Prior art date
Application number
AT06740771T
Other languages
English (en)
Inventor
Chih-Chao Yang
Lawrence Clevenger
Andrew Cowley
Timothy Dalton
Meeyoung Yoon
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE535013T1 publication Critical patent/ATE535013T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
AT06740771T 2005-04-15 2006-04-07 Verbindungsstruktur und herstellungsverfahren dafür ATE535013T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/107,074 US7335588B2 (en) 2005-04-15 2005-04-15 Interconnect structure and method of fabrication of same
PCT/US2006/013179 WO2006113186A2 (en) 2005-04-15 2006-04-07 Interconnect structure and method of fabrication of same

Publications (1)

Publication Number Publication Date
ATE535013T1 true ATE535013T1 (de) 2011-12-15

Family

ID=37109075

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06740771T ATE535013T1 (de) 2005-04-15 2006-04-07 Verbindungsstruktur und herstellungsverfahren dafür

Country Status (7)

Country Link
US (4) US7335588B2 (de)
EP (1) EP1869700B1 (de)
JP (1) JP5089575B2 (de)
CN (1) CN101390203B (de)
AT (1) ATE535013T1 (de)
TW (1) TWI389252B (de)
WO (1) WO2006113186A2 (de)

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WO2017111803A1 (en) * 2015-12-24 2017-06-29 Intel Corporation Techniques for forming electrically conductive features with improved alignment and capacitance reduction
WO2017111847A1 (en) * 2015-12-24 2017-06-29 Intel Corporation Techniques for forming electrically conductive features with improved alignment and capacitance reduction
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US10096550B2 (en) 2017-02-21 2018-10-09 Raytheon Company Nitride structure having gold-free contact and methods for forming such structures
US10224285B2 (en) 2017-02-21 2019-03-05 Raytheon Company Nitride structure having gold-free contact and methods for forming such structures
US10510657B2 (en) 2017-09-26 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with interconnecting structure and method for manufacturing the same
US11004735B2 (en) * 2018-09-14 2021-05-11 International Business Machines Corporation Conductive interconnect having a semi-liner and no top surface recess
TWI801631B (zh) * 2018-11-09 2023-05-11 台灣積體電路製造股份有限公司 半導體裝置的製造方法和半導體裝置
US11094580B2 (en) * 2019-10-01 2021-08-17 International Business Machines Corporation Structure and method to fabricate fully aligned via with reduced contact resistance
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Also Published As

Publication number Publication date
JP2008537337A (ja) 2008-09-11
WO2006113186A2 (en) 2006-10-26
CN101390203A (zh) 2009-03-18
US7563710B2 (en) 2009-07-21
JP5089575B2 (ja) 2012-12-05
US20060234497A1 (en) 2006-10-19
US20080246151A1 (en) 2008-10-09
TWI389252B (zh) 2013-03-11
US7528493B2 (en) 2009-05-05
EP1869700A4 (de) 2010-12-15
US7598616B2 (en) 2009-10-06
EP1869700A2 (de) 2007-12-26
US20080006944A1 (en) 2008-01-10
TW200636917A (en) 2006-10-16
US20080014744A1 (en) 2008-01-17
WO2006113186A3 (en) 2008-07-24
CN101390203B (zh) 2012-03-21
EP1869700B1 (de) 2011-11-23
US7335588B2 (en) 2008-02-26

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