ATE535861T1 - Verfahren und vorrichtungen zur zweigvorhersage und verarbeitung von mikroprozessoranweisungen und dergleichen - Google Patents

Verfahren und vorrichtungen zur zweigvorhersage und verarbeitung von mikroprozessoranweisungen und dergleichen

Info

Publication number
ATE535861T1
ATE535861T1 AT05793867T AT05793867T ATE535861T1 AT E535861 T1 ATE535861 T1 AT E535861T1 AT 05793867 T AT05793867 T AT 05793867T AT 05793867 T AT05793867 T AT 05793867T AT E535861 T1 ATE535861 T1 AT E535861T1
Authority
AT
Austria
Prior art keywords
storing circuit
branch prediction
aghr
processing
stage
Prior art date
Application number
AT05793867T
Other languages
English (en)
Inventor
Jeffrey Nye
Thang Tran
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE535861T1 publication Critical patent/ATE535861T1/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
AT05793867T 2004-08-30 2005-08-30 Verfahren und vorrichtungen zur zweigvorhersage und verarbeitung von mikroprozessoranweisungen und dergleichen ATE535861T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US60584604P 2004-08-30 2004-08-30
US11/210,354 US7752426B2 (en) 2004-08-30 2005-08-24 Processes, circuits, devices, and systems for branch prediction and other processor improvements
PCT/US2005/031191 WO2006057685A1 (en) 2004-08-30 2005-08-30 Methods and apparatus for branch prediction and processing of microprocessor instructions and the like

Publications (1)

Publication Number Publication Date
ATE535861T1 true ATE535861T1 (de) 2011-12-15

Family

ID=36263528

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05793867T ATE535861T1 (de) 2004-08-30 2005-08-30 Verfahren und vorrichtungen zur zweigvorhersage und verarbeitung von mikroprozessoranweisungen und dergleichen

Country Status (4)

Country Link
US (1) US7752426B2 (de)
EP (1) EP1810130B1 (de)
AT (1) ATE535861T1 (de)
WO (1) WO2006057685A1 (de)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7836288B2 (en) * 2004-09-14 2010-11-16 Arm Limited Branch prediction mechanism including a branch prediction memory and a branch prediction cache
US8155703B2 (en) * 2004-10-01 2012-04-10 Broadcom Corporation Wireless device having a configurable camera interface to support digital image processing
US7506105B2 (en) * 2005-05-02 2009-03-17 Freescale Semiconductor, Inc. Prefetching using hashed program counter
US20070101100A1 (en) * 2005-10-28 2007-05-03 Freescale Semiconductor, Inc. System and method for decoupled precomputation prefetching
US20070189160A1 (en) * 2006-02-14 2007-08-16 Itamar Landau Method and system for randomized puncturing in mobile communication systems
US7668188B2 (en) * 2006-02-14 2010-02-23 Broadcom Corporation Method and system for HSDPA bit level processor engine
US7647476B2 (en) * 2006-03-14 2010-01-12 Intel Corporation Common analog interface for multiple processor cores
US9146745B2 (en) * 2006-06-29 2015-09-29 Intel Corporation Method and apparatus for partitioned pipelined execution of multiple execution threads
US20080046684A1 (en) * 2006-08-17 2008-02-21 International Business Machines Corporation Multithreaded multicore uniprocessor and a heterogeneous multiprocessor incorporating the same
US7984279B2 (en) * 2006-11-03 2011-07-19 Qualcomm Incorporated System and method for using a working global history register
US7769909B2 (en) * 2006-12-04 2010-08-03 Atmel Corporation Device and method for access time reduction by speculatively decoding non-memory read commands on a serial interface
US8073669B2 (en) * 2007-08-21 2011-12-06 International Business Machines Corporation Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design
US7707398B2 (en) * 2007-11-13 2010-04-27 Applied Micro Circuits Corporation System and method for speculative global history prediction updating
US7937856B2 (en) * 2007-12-21 2011-05-10 Nike, Inc. Article of footwear with illuminated chamber
US10750023B2 (en) 2008-01-28 2020-08-18 Afiniti Europe Technologies Limited Techniques for hybrid behavioral pairing in a contact center system
US7937573B2 (en) * 2008-02-29 2011-05-03 Freescale Semiconductor, Inc. Metric for selective branch target buffer (BTB) allocation
US7895422B2 (en) * 2008-02-29 2011-02-22 Freescale Semiconductor, Inc. Selective postponement of branch target buffer (BTB) allocation
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
US8423751B2 (en) * 2009-03-04 2013-04-16 Via Technologies, Inc. Microprocessor with fast execution of call and return instructions
JP2010211487A (ja) * 2009-03-10 2010-09-24 Fuji Xerox Co Ltd 処理システム、処理装置及び処理プログラム
KR20120036210A (ko) * 2010-10-07 2012-04-17 삼성전자주식회사 파이프라인 제어 위험 감소를 위한 처리장치 및 컴파일 장치와, 파이프라인 제어 위험 감소를 위한 동적 조건 분기 처리 방법
US9122486B2 (en) 2010-11-08 2015-09-01 Qualcomm Incorporated Bimodal branch predictor encoded in a branch instruction
CA2840154C (en) * 2011-06-28 2017-08-15 Zte Portugal-Projectos De Telecomunicacoes Unipessoal Lda Establishing a secure file transfer session for secure file transfer to a demarcation device
US9395994B2 (en) 2011-12-30 2016-07-19 Intel Corporation Embedded branch prediction unit
US8614920B2 (en) * 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
TWI501240B (zh) * 2012-06-14 2015-09-21 Winbond Electronics Corp 快閃記憶體及操作記憶體裝置的方法
US9753733B2 (en) 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9557999B2 (en) 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US20140156978A1 (en) * 2012-11-30 2014-06-05 Muawya M. Al-Otoom Detecting and Filtering Biased Branches in Global Branch History
US9417920B2 (en) 2013-10-04 2016-08-16 Freescale Semiconductor, Inc. Method and apparatus for dynamic resource partition in simultaneous multi-thread microprocessor
JP6523274B2 (ja) * 2013-10-25 2019-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 分岐予測ユニット及びレベル１命令キャッシュにおける帯域幅の増加
US9519479B2 (en) 2013-11-18 2016-12-13 Globalfoundries Inc. Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US9612840B2 (en) * 2014-03-28 2017-04-04 Intel Corporation Method and apparatus for implementing a dynamic out-of-order processor pipeline
US10534611B2 (en) * 2014-07-31 2020-01-14 International Business Machines Corporation Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV)
US9960909B2 (en) * 2014-12-08 2018-05-01 Open-Silicon Inc. High speed and low power hashing system and method
US9934041B2 (en) 2015-07-01 2018-04-03 International Business Machines Corporation Pattern based branch prediction
US10664280B2 (en) * 2015-11-09 2020-05-26 MIPS Tech, LLC Fetch ahead branch target buffer
US10423418B2 (en) 2015-11-30 2019-09-24 International Business Machines Corporation Method for maintaining a branch prediction history table
CN113099053B (zh) * 2016-04-18 2023-03-24 阿菲尼帝有限公司 用于对联系中心系统中的配对策略进行基准检测的技术
US10592248B2 (en) * 2016-08-30 2020-03-17 Advanced Micro Devices, Inc. Branch target buffer compression
US10489296B2 (en) 2016-09-22 2019-11-26 International Business Machines Corporation Quality of cache management in a computer
CN108509791B (zh) * 2018-02-09 2021-06-04 清华大学 检测处理器的方法、检测装置以及检测系统
CN109298372A (zh) * 2018-09-05 2019-02-01 中国电力科学研究院有限公司 通信单元自动化检测流水线用工装托盘
CN109212460B (zh) * 2018-09-05 2022-09-09 中国电力科学研究院有限公司 一种通信单元检测工装及检测方法
US10838731B2 (en) * 2018-09-19 2020-11-17 Qualcomm Incorporated Branch prediction based on load-path history
US11928471B2 (en) * 2021-08-19 2024-03-12 International Business Machines Corporation Metadata predictor
CN115617402B (zh) * 2022-11-18 2023-04-07 北京数渡信息科技有限公司 一种适用于通用处理器的解耦合分支预测方法及装置
US12481592B2 (en) * 2022-12-26 2025-11-25 Nxp Usa, Inc. System and method for tracing instruction cache misses
CN116627507B (zh) * 2023-06-19 2024-04-12 海光信息技术股份有限公司 队列控制方法、装置、电子设备和计算机可读存储介质
CN117311816A (zh) * 2023-11-03 2023-12-29 北京奕斯伟计算技术股份有限公司 处理指令的方法、处理器、电子装置及存储介质
US20250245010A1 (en) * 2024-01-29 2025-07-31 Arm Limited Return address restoration

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287467A (en) 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5918046A (en) * 1994-01-03 1999-06-29 Intel Corporation Method and apparatus for a branch instruction pointer table
US5574871A (en) 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
TW253946B (en) 1994-02-04 1995-08-11 Ibm Data processor with branch prediction and method of operation
US5530825A (en) * 1994-04-15 1996-06-25 Motorola, Inc. Data processor with branch target address cache and method of operation
US5822575A (en) * 1996-09-12 1998-10-13 Advanced Micro Devices, Inc. Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
US5978906A (en) 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
DE69727773T2 (de) 1996-12-10 2004-12-30 Texas Instruments Inc., Dallas Verbesserte Verzweigungsvorhersage in einem Pipelinemikroprozessor
US6871275B1 (en) 1996-12-12 2005-03-22 Intel Corporation Microprocessor having a branch predictor using speculative branch registers
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5964870A (en) * 1997-09-22 1999-10-12 Intel Corporation Method and apparatus for using function context to improve branch
US6185676B1 (en) 1997-09-30 2001-02-06 Intel Corporation Method and apparatus for performing early branch prediction in a microprocessor
US6175946B1 (en) * 1997-10-20 2001-01-16 O-In Design Automation Method for automatically generating checkers for finding functional defects in a description of a circuit
US6081887A (en) 1998-05-13 2000-06-27 Compaq Computer Corporation System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction
US6223280B1 (en) * 1998-07-16 2001-04-24 Advanced Micro Devices, Inc. Method and circuit for preloading prediction circuits in microprocessors
US6553488B2 (en) 1998-09-08 2003-04-22 Intel Corporation Method and apparatus for branch prediction using first and second level branch prediction tables
US6189091B1 (en) 1998-12-02 2001-02-13 Ip First, L.L.C. Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
US6430674B1 (en) 1998-12-30 2002-08-06 Intel Corporation Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
US6272623B1 (en) 1999-01-25 2001-08-07 Sun Microsystems, Inc. Methods and apparatus for branch prediction using hybrid history with index sharing
KR100317240B1 (ko) 1999-10-21 2001-12-22 윤종용 분기 예측 정확도 히스토리를 이용한 분기 예측기
AU2001231244A1 (en) 2000-01-28 2001-08-07 Morphics Technology, Inc. A method of generating a configuration for a configurable spread spectrum communication device
KR100395763B1 (ko) 2000-02-01 2003-08-25 삼성전자주식회사 멀티프로세싱 마이크로프로세서에 적합한 분기 예측기
US6745323B1 (en) 2000-08-03 2004-06-01 International Business Machines Corporation Global history vector recovery circuits and methods and systems using the same
US6766441B2 (en) 2001-01-19 2004-07-20 International Business Machines Corporation Prefetching instructions in mis-predicted path for low confidence branches
US6886093B2 (en) 2001-05-04 2005-04-26 Ip-First, Llc Speculative hybrid branch direction predictor
US6898721B2 (en) * 2001-06-22 2005-05-24 Gallitzin Allegheny Llc Clock generation systems and methods
US7143273B2 (en) 2003-03-31 2006-11-28 Intel Corporation Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history
US7093111B2 (en) 2003-07-31 2006-08-15 International Business Machines Corporation Recovery of global history vector in the event of a non-branch flush
KR100980076B1 (ko) 2003-10-24 2010-09-06 삼성전자주식회사 저전력 분기 예측 시스템 및 분기 예측 방법
US7243219B2 (en) 2003-12-24 2007-07-10 Intel Corporation Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction

Also Published As

Publication number Publication date
WO2006057685A1 (en) 2006-06-01
US7752426B2 (en) 2010-07-06
EP1810130A4 (de) 2008-08-13
EP1810130B1 (de) 2011-11-30
US20060095750A1 (en) 2006-05-04
EP1810130A1 (de) 2007-07-25

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