ATE536662T1 - Phasenregelkreis mit selbstkorrigierender übertragungsfunktion von phase-zu-digital - Google Patents
Phasenregelkreis mit selbstkorrigierender übertragungsfunktion von phase-zu-digitalInfo
- Publication number
- ATE536662T1 ATE536662T1 AT08870515T AT08870515T ATE536662T1 AT E536662 T1 ATE536662 T1 AT E536662T1 AT 08870515 T AT08870515 T AT 08870515T AT 08870515 T AT08870515 T AT 08870515T AT E536662 T1 ATE536662 T1 AT E536662T1
- Authority
- AT
- Austria
- Prior art keywords
- phase
- transfer function
- pdc
- phase error
- error words
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/969,364 US7583152B2 (en) | 2008-01-04 | 2008-01-04 | Phase-locked loop with self-correcting phase-to-digital transfer function |
| PCT/US2008/088262 WO2009088789A1 (en) | 2008-01-04 | 2008-12-24 | Phase-locked loop with self-correcting phase-to-digital transfer function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE536662T1 true ATE536662T1 (de) | 2011-12-15 |
Family
ID=40428289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT08870515T ATE536662T1 (de) | 2008-01-04 | 2008-12-24 | Phasenregelkreis mit selbstkorrigierender übertragungsfunktion von phase-zu-digital |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7583152B2 (de) |
| EP (1) | EP2243222B1 (de) |
| JP (1) | JP5113263B2 (de) |
| KR (1) | KR101228395B1 (de) |
| CN (1) | CN101911494B (de) |
| AT (1) | ATE536662T1 (de) |
| TW (1) | TW200935748A (de) |
| WO (1) | WO2009088789A1 (de) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8193866B2 (en) | 2007-10-16 | 2012-06-05 | Mediatek Inc. | All-digital phase-locked loop |
| US7759993B2 (en) * | 2008-08-06 | 2010-07-20 | Qualcomm Incorporated | Accumulated phase-to-digital conversion in digital phase locked loops |
| US20100074387A1 (en) * | 2008-09-24 | 2010-03-25 | Infineon Technologies Ag | Frequency to Phase Converter with Uniform Sampling for all Digital Phase Locked Loops |
| US7893736B2 (en) * | 2008-11-14 | 2011-02-22 | Analog Devices, Inc. | Multiple input PLL with hitless switchover between non-integer related input frequencies |
| US20100123488A1 (en) * | 2008-11-14 | 2010-05-20 | Analog Devices, Inc. | Digital pll with known noise source and known loop bandwidth |
| US7924072B2 (en) * | 2008-11-14 | 2011-04-12 | Analog Devices, Inc. | Exact frequency translation using dual cascaded sigma-delta modulator controlled phase lock loops |
| US7924966B2 (en) * | 2008-11-21 | 2011-04-12 | Analog Devices, Inc. | Symmetry corrected high frequency digital divider |
| US8138840B2 (en) * | 2009-01-23 | 2012-03-20 | International Business Machines Corporation | Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control |
| US7816959B1 (en) * | 2009-02-23 | 2010-10-19 | Integrated Device Technology, Inc. | Clock circuit for reducing long term jitter |
| TWI502308B (zh) * | 2009-07-09 | 2015-10-01 | Univ Nat Taiwan | 全數位展頻時脈產生器 |
| US8446191B2 (en) * | 2009-12-07 | 2013-05-21 | Qualcomm Incorporated | Phase locked loop with digital compensation for analog integration |
| US8339165B2 (en) | 2009-12-07 | 2012-12-25 | Qualcomm Incorporated | Configurable digital-analog phase locked loop |
| JP2011205328A (ja) * | 2010-03-25 | 2011-10-13 | Toshiba Corp | 局部発振器 |
| US8248106B1 (en) | 2010-07-21 | 2012-08-21 | Applied Micro Circuits Corporation | Lock detection using a digital phase error message |
| CN102457292B (zh) * | 2010-10-19 | 2014-07-02 | 中国移动通信集团公司 | 一种终端设备 |
| US8390347B1 (en) * | 2012-02-22 | 2013-03-05 | Freescale Semiconductor, Inc. | Single period phase to digital converter |
| KR101328372B1 (ko) | 2012-02-27 | 2013-11-11 | 삼성전기주식회사 | 전폭 디지털 위상 제어기 및 방법 |
| US9014322B2 (en) * | 2012-05-23 | 2015-04-21 | Finisar Corporation | Low power and compact area digital integrator for a digital phase detector |
| US8957712B2 (en) * | 2013-03-15 | 2015-02-17 | Qualcomm Incorporated | Mixed signal TDC with embedded T2V ADC |
| KR20140113216A (ko) | 2013-03-15 | 2014-09-24 | 삼성전자주식회사 | 위상-디지털 컨버터를 이용한 디지털 위상 동기 루프 회로, 그 동작 방법 및 이를 포함하는 장치 |
| KR101483855B1 (ko) * | 2013-04-22 | 2015-01-16 | 삼성전기주식회사 | Pll 다이렉트 모듈레이터 및 그 모듈레이터에서의 주파수 이득 부정합 보상 방법 |
| US8723568B1 (en) * | 2013-12-20 | 2014-05-13 | Qualcomm Incorporated | Local oscillator signal generation using delay locked loops |
| US10003346B2 (en) * | 2015-03-20 | 2018-06-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Fractional PLLs with low correlation |
| US10224940B2 (en) | 2015-04-27 | 2019-03-05 | Telefonaktiebolaget Lm Ericsson (Publ) | Digital phase controlled PLLs |
| CN106655844A (zh) * | 2016-09-28 | 2017-05-10 | 广东电网有限责任公司电力科学研究院 | 一种基于全数字锁相环的谐振电流相位控制器及方法 |
| US10305495B2 (en) * | 2016-10-06 | 2019-05-28 | Analog Devices, Inc. | Phase control of clock signal based on feedback |
| TWI646772B (zh) * | 2017-05-24 | 2019-01-01 | 金麗科技股份有限公司 | 相位校正電路與相位校正方法 |
| CN109283832B (zh) * | 2018-09-14 | 2020-05-12 | 东北大学 | 一种低功耗的时间数字转换器及其phv补偿方法 |
| US10819355B1 (en) | 2019-09-24 | 2020-10-27 | Nxp Usa, Inc. | Phase to digital converter |
| TWI757125B (zh) * | 2020-05-18 | 2022-03-01 | 瑞昱半導體股份有限公司 | 自校準的低雜訊工作週期校正電路及其方法 |
| US11784651B2 (en) * | 2021-10-27 | 2023-10-10 | Nxp B.V. | Circuitry and methods for fractional division of high-frequency clock signals |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU8958282A (en) * | 1982-05-19 | 1983-12-02 | Vicino, R.K. | Inflatable display structure |
| JPH07120942B2 (ja) * | 1985-11-27 | 1995-12-20 | 株式会社日立製作所 | Pll回路 |
| US4752748A (en) * | 1987-04-16 | 1988-06-21 | Amdahl Corporation | Intelligent phase-locked loop |
| DE4303356A1 (de) * | 1993-02-05 | 1994-08-11 | Philips Patentverwaltung | Digitale Phasenregelschleife |
| JP3458494B2 (ja) * | 1993-12-24 | 2003-10-20 | ソニー株式会社 | クロック信号再生回路およびデータ再生回路 |
| US5486792A (en) * | 1995-03-06 | 1996-01-23 | Motorola, Inc. | Method and apparatus for calculating a divider in a digital phase lock loop |
| JPH10322198A (ja) * | 1997-05-14 | 1998-12-04 | Nec Corp | フェーズロックドループ回路 |
| US6236275B1 (en) * | 1997-10-24 | 2001-05-22 | Ericsson Inc. | Digital frequency synthesis by sequential fraction approximations |
| JP3895028B2 (ja) * | 1997-12-26 | 2007-03-22 | 日本テキサス・インスツルメンツ株式会社 | 周波数シンセサイザ |
| US6826247B1 (en) * | 2000-03-24 | 2004-11-30 | Stmicroelectronics, Inc. | Digital phase lock loop |
| US6851493B2 (en) * | 2000-12-01 | 2005-02-08 | Texas Instruments Incorporated | Digital PLL with gear shift |
| US7148760B2 (en) * | 2004-12-30 | 2006-12-12 | Nokia Corporation | VCO gain tuning using voltage measurements and frequency iteration |
| DE102005023909B3 (de) * | 2005-05-24 | 2006-10-12 | Infineon Technologies Ag | Digitaler Phasenregelkreis und Verfahren zur Korrektur von Störanteilen in einem Phasenregelkreis |
| US7403073B2 (en) | 2005-09-30 | 2008-07-22 | International Business Machines Corporation | Phase locked loop and method for adjusting the frequency and phase in the phase locked loop |
| JP4252605B2 (ja) * | 2006-02-24 | 2009-04-08 | 日本電波工業株式会社 | Pll回路 |
-
2008
- 2008-01-04 US US11/969,364 patent/US7583152B2/en active Active
- 2008-12-24 CN CN2008801237426A patent/CN101911494B/zh active Active
- 2008-12-24 AT AT08870515T patent/ATE536662T1/de active
- 2008-12-24 JP JP2010541499A patent/JP5113263B2/ja active Active
- 2008-12-24 EP EP08870515A patent/EP2243222B1/de active Active
- 2008-12-24 WO PCT/US2008/088262 patent/WO2009088789A1/en not_active Ceased
- 2008-12-24 KR KR1020107017356A patent/KR101228395B1/ko not_active Expired - Fee Related
- 2008-12-31 TW TW097151667A patent/TW200935748A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR101228395B1 (ko) | 2013-01-31 |
| WO2009088789A1 (en) | 2009-07-16 |
| CN101911494B (zh) | 2013-06-26 |
| KR20100101005A (ko) | 2010-09-15 |
| EP2243222B1 (de) | 2011-12-07 |
| JP2011509047A (ja) | 2011-03-17 |
| TW200935748A (en) | 2009-08-16 |
| EP2243222A1 (de) | 2010-10-27 |
| JP5113263B2 (ja) | 2013-01-09 |
| CN101911494A (zh) | 2010-12-08 |
| US7583152B2 (en) | 2009-09-01 |
| US20090174492A1 (en) | 2009-07-09 |
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