ATE538435T1 - Speichersteuerung und verfahren zum koppeln eines netzwerkes und eines speichers - Google Patents

Speichersteuerung und verfahren zum koppeln eines netzwerkes und eines speichers

Info

Publication number
ATE538435T1
ATE538435T1 AT06756100T AT06756100T ATE538435T1 AT E538435 T1 ATE538435 T1 AT E538435T1 AT 06756100 T AT06756100 T AT 06756100T AT 06756100 T AT06756100 T AT 06756100T AT E538435 T1 ATE538435 T1 AT E538435T1
Authority
AT
Austria
Prior art keywords
memory
network
network interface
data
tpb
Prior art date
Application number
AT06756100T
Other languages
English (en)
Inventor
Artur Burchard
Ewa Hekstra-Nowacka
Den Hamer Peter Van
Atul Chauhan
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE538435T1 publication Critical patent/ATE538435T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
AT06756100T 2005-06-09 2006-06-09 Speichersteuerung und verfahren zum koppeln eines netzwerkes und eines speichers ATE538435T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05105094 2005-06-09
PCT/IB2006/051842 WO2006131900A2 (en) 2005-06-09 2006-06-09 Memory controller and method for coupling a network and a memory

Publications (1)

Publication Number Publication Date
ATE538435T1 true ATE538435T1 (de) 2012-01-15

Family

ID=37075836

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06756100T ATE538435T1 (de) 2005-06-09 2006-06-09 Speichersteuerung und verfahren zum koppeln eines netzwerkes und eines speichers

Country Status (6)

Country Link
US (1) US8065493B2 (de)
EP (1) EP1894107B1 (de)
JP (1) JP2008542904A (de)
CN (1) CN101194242A (de)
AT (1) ATE538435T1 (de)
WO (1) WO2006131900A2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7987469B2 (en) 2006-12-14 2011-07-26 Intel Corporation RDMA (remote direct memory access) data transfer in a virtual environment
US7836198B2 (en) * 2008-03-20 2010-11-16 International Business Machines Corporation Ethernet virtualization using hardware control flow override
US9489326B1 (en) * 2009-03-09 2016-11-08 Cypress Semiconductor Corporation Multi-port integrated circuit devices and methods
US20100228926A1 (en) * 2009-03-09 2010-09-09 Cypress Semiconductor Corporation Multi-port memory devices and methods
US8683128B2 (en) 2010-05-07 2014-03-25 International Business Machines Corporation Memory bus write prioritization
US8838901B2 (en) * 2010-05-07 2014-09-16 International Business Machines Corporation Coordinated writeback of dirty cachelines
US20120066444A1 (en) * 2010-09-14 2012-03-15 Advanced Micro Devices, Inc. Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation
FR2982049B1 (fr) * 2011-10-28 2014-02-28 Kalray Gestion de flux dans un reseau sur puce
US9542345B2 (en) * 2012-09-28 2017-01-10 Apple Inc. Interrupt suppression strategy
US10996888B2 (en) * 2017-10-31 2021-05-04 Qualcomm Incorporated Write credits management for non-volatile memory
JP7598895B2 (ja) * 2022-03-24 2024-12-12 日立ヴァンタラ株式会社 ネットワークインタフェース及びそのバッファ制御方法
US20240086346A1 (en) * 2022-09-08 2024-03-14 Sunrise Memory Corporation Dynamic random-access memory (dram) configured for block transfers and method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2797969A1 (fr) * 1999-08-31 2001-03-02 Koninkl Philips Electronics Nv Dispositif a plusieurs processeurs partageant une memoire collective
US6557053B1 (en) * 2000-01-04 2003-04-29 International Business Machines Corporation Queue manager for a buffer
US20020046251A1 (en) * 2001-03-09 2002-04-18 Datacube, Inc. Streaming memory controller
US7555566B2 (en) * 2001-02-24 2009-06-30 International Business Machines Corporation Massively parallel supercomputer
JP2007503042A (ja) * 2003-08-20 2007-02-15 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 動的メモリバッファ
WO2006059283A2 (en) * 2004-12-03 2006-06-08 Koninklijke Philips Electronics N.V. Streaming memory controller
WO2006134550A2 (en) * 2005-06-13 2006-12-21 Nxp B.V. Memory controller

Also Published As

Publication number Publication date
JP2008542904A (ja) 2008-11-27
EP1894107B1 (de) 2011-12-21
CN101194242A (zh) 2008-06-04
US8065493B2 (en) 2011-11-22
WO2006131900A2 (en) 2006-12-14
US20090083500A1 (en) 2009-03-26
EP1894107A2 (de) 2008-03-05
WO2006131900A3 (en) 2007-04-26

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