ATE538494T1 - Verfahren zur herstellung eines ssoi-substrats - Google Patents
Verfahren zur herstellung eines ssoi-substratsInfo
- Publication number
- ATE538494T1 ATE538494T1 AT08162465T AT08162465T ATE538494T1 AT E538494 T1 ATE538494 T1 AT E538494T1 AT 08162465 T AT08162465 T AT 08162465T AT 08162465 T AT08162465 T AT 08162465T AT E538494 T1 ATE538494 T1 AT E538494T1
- Authority
- AT
- Austria
- Prior art keywords
- substrate
- sige
- layer
- sige layer
- ssoi
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070083630A KR100873299B1 (ko) | 2007-08-20 | 2007-08-20 | Ｓｓｏｉ 기판의 제조방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE538494T1 true ATE538494T1 (de) | 2012-01-15 |
Family
ID=39967379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT08162465T ATE538494T1 (de) | 2007-08-20 | 2008-08-15 | Verfahren zur herstellung eines ssoi-substrats |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7906408B2 (de) |
| EP (1) | EP2028685B1 (de) |
| JP (1) | JP5697839B2 (de) |
| KR (1) | KR100873299B1 (de) |
| CN (1) | CN101373710B (de) |
| AT (1) | ATE538494T1 (de) |
| TW (1) | TWI470744B (de) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100044827A1 (en) * | 2008-08-22 | 2010-02-25 | Kinik Company | Method for making a substrate structure comprising a film and substrate structure made by same method |
| EP2282332B1 (de) * | 2009-08-04 | 2012-06-27 | S.O.I. TEC Silicon | Herstellungsverfahren eines Halbleitersubstrat |
| EP2333824B1 (de) * | 2009-12-11 | 2014-04-16 | Soitec | Herstellung von dünnen SOI-Vorrichtungen |
| US7935612B1 (en) * | 2010-02-05 | 2011-05-03 | International Business Machines Corporation | Layer transfer using boron-doped SiGe layer |
| CN103165512A (zh) * | 2011-12-14 | 2013-06-19 | 中国科学院上海微系统与信息技术研究所 | 一种超薄绝缘体上半导体材料及其制备方法 |
| CN103311172A (zh) | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Soi衬底的形成方法 |
| CN103441132A (zh) * | 2013-07-10 | 2013-12-11 | 上海新储集成电路有限公司 | 一种用低温裂片硅晶圆制备背照射cmos图像传感器的方法 |
| CN105097437A (zh) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 形成应变硅层的方法、pmos器件的制作方法及半导体器件 |
| US10658474B2 (en) * | 2018-08-14 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming thin semiconductor-on-insulator (SOI) substrates |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
| US6150239A (en) * | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
| US20020187619A1 (en) * | 2001-05-04 | 2002-12-12 | International Business Machines Corporation | Gettering process for bonded SOI wafers |
| JP2003078116A (ja) | 2001-08-31 | 2003-03-14 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
| JP2003347229A (ja) * | 2002-05-31 | 2003-12-05 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
| US6979630B2 (en) * | 2002-08-08 | 2005-12-27 | Isonics Corporation | Method and apparatus for transferring a thin layer of semiconductor material |
| FR2847076B1 (fr) * | 2002-11-07 | 2005-02-18 | Soitec Silicon On Insulator | Procede de detachement d'une couche mince a temperature moderee apres co-implantation |
| EP1627454A4 (de) * | 2003-05-29 | 2007-04-25 | Applied Materials Inc | Auf verunreinigungen basierende wellenleiterdetektoren |
| KR100596093B1 (ko) * | 2003-12-17 | 2006-06-30 | 주식회사 실트론 | 에스오아이 웨이퍼의 제조 방법 |
| KR100584124B1 (ko) * | 2003-12-26 | 2006-05-30 | 한국전자통신연구원 | 반도체 소자용 기판 제조 방법 및 이를 이용한 반도체소자의 제조방법 |
| US6992025B2 (en) | 2004-01-12 | 2006-01-31 | Sharp Laboratories Of America, Inc. | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation |
| US6982208B2 (en) * | 2004-05-03 | 2006-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for producing high throughput strained-Si channel MOSFETS |
| US7241670B2 (en) * | 2004-09-07 | 2007-07-10 | Sharp Laboratories Of America, Inc | Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen |
| US7202124B2 (en) * | 2004-10-01 | 2007-04-10 | Massachusetts Institute Of Technology | Strained gettering layers for semiconductor processes |
| KR100593747B1 (ko) * | 2004-10-11 | 2006-06-28 | 삼성전자주식회사 | 실리콘게르마늄층을 구비하는 반도체 구조물 및 그 제조방법 |
| JP4773101B2 (ja) * | 2005-01-12 | 2011-09-14 | 株式会社日立製作所 | 半導体装置の製造方法 |
| FR2880988B1 (fr) * | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE |
| JP4613656B2 (ja) * | 2005-03-22 | 2011-01-19 | 信越半導体株式会社 | 半導体ウエーハの製造方法 |
| EP1763069B1 (de) * | 2005-09-07 | 2016-04-13 | Soitec | Herstellungsverfahren einer Heterostruktur |
| US7153761B1 (en) * | 2005-10-03 | 2006-12-26 | Los Alamos National Security, Llc | Method of transferring a thin crystalline semiconductor layer |
| EP1777735A3 (de) * | 2005-10-18 | 2009-08-19 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zur Wiederverwendung eines temporären epitaxialen Substrates |
| FR2902233B1 (fr) * | 2006-06-09 | 2008-10-17 | Soitec Silicon On Insulator | Procede de limitation de diffusion en mode lacunaire dans une heterostructure |
-
2007
- 2007-08-20 KR KR1020070083630A patent/KR100873299B1/ko active Active
-
2008
- 2008-08-14 JP JP2008209039A patent/JP5697839B2/ja active Active
- 2008-08-15 EP EP08162465A patent/EP2028685B1/de active Active
- 2008-08-15 AT AT08162465T patent/ATE538494T1/de active
- 2008-08-20 TW TW97131791A patent/TWI470744B/zh active
- 2008-08-20 US US12/195,229 patent/US7906408B2/en active Active
- 2008-08-20 CN CN2008101471321A patent/CN101373710B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP5697839B2 (ja) | 2015-04-08 |
| CN101373710A (zh) | 2009-02-25 |
| TW200919648A (en) | 2009-05-01 |
| CN101373710B (zh) | 2012-12-05 |
| EP2028685A1 (de) | 2009-02-25 |
| US20090053875A1 (en) | 2009-02-26 |
| TWI470744B (zh) | 2015-01-21 |
| EP2028685B1 (de) | 2011-12-21 |
| JP2009049411A (ja) | 2009-03-05 |
| US7906408B2 (en) | 2011-03-15 |
| KR100873299B1 (ko) | 2008-12-11 |
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