ATE438196T1 - Verfahren zur herstellung einer relaxierten sige- schicht - Google Patents

Verfahren zur herstellung einer relaxierten sige- schicht

Info

Publication number
ATE438196T1
ATE438196T1 AT05797345T AT05797345T ATE438196T1 AT E438196 T1 ATE438196 T1 AT E438196T1 AT 05797345 T AT05797345 T AT 05797345T AT 05797345 T AT05797345 T AT 05797345T AT E438196 T1 ATE438196 T1 AT E438196T1
Authority
AT
Austria
Prior art keywords
buffer layer
layer
producing
sige layer
sige buffer
Prior art date
Application number
AT05797345T
Other languages
English (en)
Inventor
Bartlomiej Pawlak
P Meunier-Beillard
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE438196T1 publication Critical patent/ATE438196T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3822—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing

Landscapes

  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)
  • Physical Vapour Deposition (AREA)
  • Bipolar Transistors (AREA)
AT05797345T 2004-11-02 2005-10-28 Verfahren zur herstellung einer relaxierten sige- schicht ATE438196T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0424290.5A GB0424290D0 (en) 2004-11-02 2004-11-02 Method of growing a strained layer
PCT/IB2005/053523 WO2006048800A1 (en) 2004-11-02 2005-10-28 Method of growing a strained layer

Publications (1)

Publication Number Publication Date
ATE438196T1 true ATE438196T1 (de) 2009-08-15

Family

ID=33515953

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05797345T ATE438196T1 (de) 2004-11-02 2005-10-28 Verfahren zur herstellung einer relaxierten sige- schicht

Country Status (10)

Country Link
US (1) US7785993B2 (de)
EP (1) EP1810320B1 (de)
JP (1) JP2008519428A (de)
KR (1) KR20070074591A (de)
CN (1) CN100492590C (de)
AT (1) ATE438196T1 (de)
DE (1) DE602005015746D1 (de)
GB (1) GB0424290D0 (de)
TW (1) TW200623239A (de)
WO (1) WO2006048800A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
CN102427068B (zh) * 2011-12-02 2014-06-18 中国科学院上海微系统与信息技术研究所 单片集成具有晶格失配的晶体模板及其制作方法
CN103165420B (zh) * 2011-12-14 2015-11-18 中国科学院上海微系统与信息技术研究所 一种SiGe中嵌入超晶格制备应变Si的方法
CN103632930B (zh) * 2012-08-28 2016-06-15 中国科学院上海微系统与信息技术研究所 利用超薄层吸附制备绝缘体上超薄改性材料的方法
KR102130056B1 (ko) 2013-11-15 2020-07-03 삼성전자주식회사 핀 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
EP3221885B1 (de) * 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. Hochresistiver halbleiter-auf-isolator-wafer und verfahren zur herstellung
US9570298B1 (en) 2015-12-09 2017-02-14 International Business Machines Corporation Localized elastic strain relaxed buffer
JP6493197B2 (ja) * 2015-12-18 2019-04-03 株式会社Sumco シリコンゲルマニウムエピタキシャルウェーハの製造方法およびシリコンゲルマニウムエピタキシャルウェーハ
US9831324B1 (en) 2016-08-12 2017-11-28 International Business Machines Corporation Self-aligned inner-spacer replacement process using implantation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US87119A (en) * 1869-02-23 Improved tanners leach
US115888A (en) * 1871-06-13 John pfeifeb
JPS5768015A (en) * 1980-10-16 1982-04-26 Toshiba Corp Manufacture of semiconductor device
GB8522833D0 (en) * 1985-09-16 1985-10-23 Exxon Chemical Patents Inc Dithiophosphonates
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6746902B2 (en) 2002-01-31 2004-06-08 Sharp Laboratories Of America, Inc. Method to form relaxed sige layer with high ge content
US6703293B2 (en) * 2002-07-11 2004-03-09 Sharp Laboratories Of America, Inc. Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates
US6858506B2 (en) 2002-08-08 2005-02-22 Macronix International Co., Ltd. Method for fabricating locally strained channel
JP2004103805A (ja) * 2002-09-09 2004-04-02 Sharp Corp 半導体基板の製造方法、半導体基板及び半導体装置
US6825102B1 (en) * 2003-09-18 2004-11-30 International Business Machines Corporation Method of improving the quality of defective semiconductor material
US6872641B1 (en) * 2003-09-23 2005-03-29 International Business Machines Corporation Strained silicon on relaxed sige film with uniform misfit dislocation density

Also Published As

Publication number Publication date
DE602005015746D1 (de) 2009-09-10
TW200623239A (en) 2006-07-01
US20090042374A1 (en) 2009-02-12
JP2008519428A (ja) 2008-06-05
CN100492590C (zh) 2009-05-27
CN101053064A (zh) 2007-10-10
WO2006048800A1 (en) 2006-05-11
EP1810320A1 (de) 2007-07-25
US7785993B2 (en) 2010-08-31
EP1810320B1 (de) 2009-07-29
GB0424290D0 (en) 2004-12-01
KR20070074591A (ko) 2007-07-12

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