ATE542144T1 - Datenschutz auf einer integrierten schaltung - Google Patents

Datenschutz auf einer integrierten schaltung

Info

Publication number
ATE542144T1
ATE542144T1 AT09013487T AT09013487T ATE542144T1 AT E542144 T1 ATE542144 T1 AT E542144T1 AT 09013487 T AT09013487 T AT 09013487T AT 09013487 T AT09013487 T AT 09013487T AT E542144 T1 ATE542144 T1 AT E542144T1
Authority
AT
Austria
Prior art keywords
integrated circuit
reset
mode
data blocks
registers
Prior art date
Application number
AT09013487T
Other languages
English (en)
Inventor
Amar Guettaf
Love Kothari
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE542144T1 publication Critical patent/ATE542144T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT09013487T 2008-10-28 2009-10-26 Datenschutz auf einer integrierten schaltung ATE542144T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/259,903 US8074132B2 (en) 2008-10-28 2008-10-28 Protecting data on integrated circuit

Publications (1)

Publication Number Publication Date
ATE542144T1 true ATE542144T1 (de) 2012-02-15

Family

ID=41683188

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09013487T ATE542144T1 (de) 2008-10-28 2009-10-26 Datenschutz auf einer integrierten schaltung

Country Status (5)

Country Link
US (1) US8074132B2 (de)
EP (1) EP2182373B1 (de)
CN (1) CN101847446B (de)
AT (1) ATE542144T1 (de)
TW (1) TWI410653B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130329553A1 (en) * 2012-06-06 2013-12-12 Mosys, Inc. Traffic metering and shaping for network packets
US8527825B2 (en) 2010-09-21 2013-09-03 Qualcomm Incorporated Debugger based memory dump using built in self test
US9744826B2 (en) 2013-05-31 2017-08-29 Fox Factory, Inc. Methods and apparatus for adjusting a spring pre-load
CN105738800B (zh) * 2016-01-30 2018-09-04 大连理工大学 基于单双跳变的低功耗确定性bist及种子压缩方法
CN108073832B (zh) * 2016-11-15 2021-06-29 华为技术有限公司 一种数据安全保护方法及设备
US10222417B1 (en) * 2016-11-28 2019-03-05 Cadence Design Systems, Inc. Securing access to integrated circuit scan mode and data
US10481205B2 (en) 2017-07-27 2019-11-19 Seagate Technology Llc Robust secure testing of integrated circuits
US11480613B2 (en) * 2020-12-18 2022-10-25 Arm Limited Method and/or system for testing devices in non-secured environment
US11940494B2 (en) * 2021-11-11 2024-03-26 Samsung Electronics Co., Ltd. System on chip for performing scan test and method of designing the same
CN118711634B (zh) * 2023-03-20 2025-10-03 长鑫存储技术有限公司 一种写入电路、写入方法和存储器
US12493075B1 (en) 2024-06-06 2025-12-09 Stmicroelectronics International N.V. Test pattern reset control circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000073809A1 (en) * 1999-05-26 2000-12-07 Hitachi, Ltd. Semiconductor integrated circuit
US7185249B2 (en) * 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
JP3671948B2 (ja) * 2002-09-24 2005-07-13 ソニー株式会社 半導体集積回路とその試験方法
EP1560033A1 (de) * 2004-01-29 2005-08-03 STMicroelectronics S.A. Integrierte Schaltung mit sicherem Testmodus mittels Initialisierung des Testmodus
US7490231B2 (en) * 2004-07-23 2009-02-10 Broadcom Corporation Method and system for blocking data in scan registers from being shifted out of a device
US7363564B2 (en) * 2005-07-15 2008-04-22 Seagate Technology Llc Method and apparatus for securing communications ports in an electronic device
JP4262265B2 (ja) * 2006-06-20 2009-05-13 キヤノン株式会社 半導体集積回路

Also Published As

Publication number Publication date
CN101847446A (zh) 2010-09-29
EP2182373A1 (de) 2010-05-05
TW201031939A (en) 2010-09-01
EP2182373B1 (de) 2012-01-18
TWI410653B (zh) 2013-10-01
HK1148107A1 (zh) 2011-08-26
CN101847446B (zh) 2013-03-20
US8074132B2 (en) 2011-12-06
US20100107023A1 (en) 2010-04-29

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