ATE545869T1 - Schaltung mit einem testfähigen schaltkreis an einen privilegierten informationslieferungsschaltkreis gekoppelt - Google Patents

Schaltung mit einem testfähigen schaltkreis an einen privilegierten informationslieferungsschaltkreis gekoppelt

Info

Publication number
ATE545869T1
ATE545869T1 AT09786798T AT09786798T ATE545869T1 AT E545869 T1 ATE545869 T1 AT E545869T1 AT 09786798 T AT09786798 T AT 09786798T AT 09786798 T AT09786798 T AT 09786798T AT E545869 T1 ATE545869 T1 AT E545869T1
Authority
AT
Austria
Prior art keywords
circuit
testable
coupled
privileged information
test
Prior art date
Application number
AT09786798T
Other languages
English (en)
Inventor
Hubertus Gerardus Hendrikus Vermeulen
Andre Krijn Nieuwland
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE545869T1 publication Critical patent/ATE545869T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT09786798T 2008-08-08 2009-08-04 Schaltung mit einem testfähigen schaltkreis an einen privilegierten informationslieferungsschaltkreis gekoppelt ATE545869T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08162115 2008-08-08
PCT/IB2009/053388 WO2010016004A1 (en) 2008-08-08 2009-08-04 Circuit with testable circuit coupled to privileged information supply circuit

Publications (1)

Publication Number Publication Date
ATE545869T1 true ATE545869T1 (de) 2012-03-15

Family

ID=41212205

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09786798T ATE545869T1 (de) 2008-08-08 2009-08-04 Schaltung mit einem testfähigen schaltkreis an einen privilegierten informationslieferungsschaltkreis gekoppelt

Country Status (5)

Country Link
US (1) US8707443B2 (de)
EP (1) EP2316041B1 (de)
CN (1) CN102112889A (de)
AT (1) ATE545869T1 (de)
WO (1) WO2010016004A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017208591A1 (de) 2017-05-22 2018-11-22 Robert Bosch Gmbh Kontrolleinheit zum Vergleichen eines eingegebenen Passworts mit einem hinterlegten Passwort
CN110554305B (zh) * 2019-09-09 2021-11-09 龙芯中科技术股份有限公司 测试控制装置、芯片及方法
US11940494B2 (en) * 2021-11-11 2024-03-26 Samsung Electronics Co., Ltd. System on chip for performing scan test and method of designing the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357572A (en) 1992-09-22 1994-10-18 Hughes Aircraft Company Apparatus and method for sensitive circuit protection with set-scan testing
DE4321151C1 (de) * 1993-06-25 1994-11-24 Adm Technology Corp Schutzschlüssel-Schaltkreis
US6499124B1 (en) * 1999-05-06 2002-12-24 Xilinx, Inc. Intest security circuit for boundary-scan architecture
JP3856651B2 (ja) * 2001-01-29 2006-12-13 松下電器産業株式会社 半導体装置
US7185249B2 (en) 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
JP3671948B2 (ja) * 2002-09-24 2005-07-13 ソニー株式会社 半導体集積回路とその試験方法
DE60306952T2 (de) * 2002-11-18 2007-02-08 Arm Ltd., Cherry Hinton Zuordnung von virtuellen zu physischen speicheradressen in einem system mit einem sicheren bereich und einem nicht sicheren bereich
EP1439398A1 (de) 2003-01-16 2004-07-21 STMicroelectronics Limited Scan Test Anordnung
ATE377197T1 (de) * 2003-09-19 2007-11-15 Nxp Bv Elektronische schaltung mit einem geheimen submodul
EP1560033A1 (de) * 2004-01-29 2005-08-03 STMicroelectronics S.A. Integrierte Schaltung mit sicherem Testmodus mittels Initialisierung des Testmodus
US7380281B2 (en) * 2004-05-06 2008-05-27 International Business Machines Corporation System and method for automatically hiding sensitive information obtainable from a process table
WO2007017838A1 (en) * 2005-08-10 2007-02-15 Nxp B.V. Testing of an integrated circuit that contains secret information
JP4262265B2 (ja) * 2006-06-20 2009-05-13 キヤノン株式会社 半導体集積回路
US7640280B2 (en) * 2006-10-31 2009-12-29 Rebit, Inc. System for automatically shadowing data and file directory structures that are recorded on a computer memory
US8775824B2 (en) * 2008-01-02 2014-07-08 Arm Limited Protecting the security of secure data sent from a central processor for processing by a further processing device

Also Published As

Publication number Publication date
EP2316041A1 (de) 2011-05-04
US8707443B2 (en) 2014-04-22
EP2316041B1 (de) 2012-02-15
CN102112889A (zh) 2011-06-29
WO2010016004A1 (en) 2010-02-11
US20110173702A1 (en) 2011-07-14

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