ATE377197T1 - Elektronische schaltung mit einem geheimen submodul - Google Patents

Elektronische schaltung mit einem geheimen submodul

Info

Publication number
ATE377197T1
ATE377197T1 AT04769376T AT04769376T ATE377197T1 AT E377197 T1 ATE377197 T1 AT E377197T1 AT 04769376 T AT04769376 T AT 04769376T AT 04769376 T AT04769376 T AT 04769376T AT E377197 T1 ATE377197 T1 AT E377197T1
Authority
AT
Austria
Prior art keywords
secret
sub
scan chains
electronic circuit
module
Prior art date
Application number
AT04769376T
Other languages
English (en)
Inventor
Jean-Marc Yannou
Herve Fleury
Herve Vincent
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE377197T1 publication Critical patent/ATE377197T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
AT04769376T 2003-09-19 2004-09-10 Elektronische schaltung mit einem geheimen submodul ATE377197T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03300125 2003-09-19

Publications (1)

Publication Number Publication Date
ATE377197T1 true ATE377197T1 (de) 2007-11-15

Family

ID=34354616

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04769376T ATE377197T1 (de) 2003-09-19 2004-09-10 Elektronische schaltung mit einem geheimen submodul

Country Status (8)

Country Link
US (1) US7519496B2 (de)
EP (1) EP1678513B1 (de)
JP (1) JP2007506088A (de)
KR (1) KR20060095969A (de)
CN (1) CN100559203C (de)
AT (1) ATE377197T1 (de)
DE (1) DE602004009817T2 (de)
WO (1) WO2005029105A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8539292B2 (en) * 2005-08-10 2013-09-17 Nxp B.V. Testing of an integrated circuit that contains secret information
EP2316041B1 (de) * 2008-08-08 2012-02-15 Nxp B.V. Schaltung mit einem testfähigen schaltkreis an einen privilegierten informationslieferungsschaltkreis gekoppelt
KR20110044905A (ko) * 2008-08-15 2011-05-02 메리맥 파마슈티컬즈, 인크. 치료제에 대한 세포의 반응을 예측하는 방법 및 시스템
US10628275B2 (en) * 2018-03-07 2020-04-21 Nxp B.V. Runtime software-based self-test with mutual inter-core checking
US12412014B1 (en) * 2022-08-31 2025-09-09 Cadence Design Systems, Inc. IC chip with IC design modification detection

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US5357572A (en) * 1992-09-22 1994-10-18 Hughes Aircraft Company Apparatus and method for sensitive circuit protection with set-scan testing
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5991909A (en) * 1996-10-15 1999-11-23 Mentor Graphics Corporation Parallel decompressor and related methods and apparatuses
EP0992809A1 (de) * 1998-09-28 2000-04-12 Siemens Aktiengesellschaft Schaltungsanordnung mit deaktivierbarem Scanpfad
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
DE10038327A1 (de) * 2000-08-05 2002-02-14 Philips Corp Intellectual Pty Integrierter Schaltkreis mit Selbsttest-Schaltung
JP3937034B2 (ja) * 2000-12-13 2007-06-27 株式会社日立製作所 半導体集積回路のテスト方法及びテストパターン発生回路
US6701476B2 (en) * 2001-05-29 2004-03-02 Motorola, Inc. Test access mechanism for supporting a configurable built-in self-test circuit and method thereof
US6788078B2 (en) * 2001-11-16 2004-09-07 Delaware Capital Formation, Inc. Apparatus for scan testing printed circuit boards
JP2003234409A (ja) * 2002-02-08 2003-08-22 Matsushita Electric Ind Co Ltd 半導体集積回路
US7185249B2 (en) * 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
US7085978B2 (en) * 2002-09-17 2006-08-01 Arm Limited Validating test signal connections within an integrated circuit
EP1439398A1 (de) * 2003-01-16 2004-07-21 STMicroelectronics Limited Scan Test Anordnung

Also Published As

Publication number Publication date
EP1678513B1 (de) 2007-10-31
CN1894591A (zh) 2007-01-10
KR20060095969A (ko) 2006-09-05
US7519496B2 (en) 2009-04-14
DE602004009817T2 (de) 2008-08-21
CN100559203C (zh) 2009-11-11
EP1678513A1 (de) 2006-07-12
US20070088519A1 (en) 2007-04-19
WO2005029105A1 (en) 2005-03-31
DE602004009817D1 (de) 2007-12-13
JP2007506088A (ja) 2007-03-15

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties