ATE552557T1 - Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale - Google Patents

Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale

Info

Publication number
ATE552557T1
ATE552557T1 AT09717759T AT09717759T ATE552557T1 AT E552557 T1 ATE552557 T1 AT E552557T1 AT 09717759 T AT09717759 T AT 09717759T AT 09717759 T AT09717759 T AT 09717759T AT E552557 T1 ATE552557 T1 AT E552557T1
Authority
AT
Austria
Prior art keywords
memory
clock signal
dual
interface pin
memory architecture
Prior art date
Application number
AT09717759T
Other languages
English (en)
Inventor
Jian Mao
Raghu Sankuratri
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE552557T1 publication Critical patent/ATE552557T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
AT09717759T 2008-02-29 2009-02-04 Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale ATE552557T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/039,908 US7804735B2 (en) 2008-02-29 2008-02-29 Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals
PCT/US2009/033018 WO2009111125A1 (en) 2008-02-29 2009-02-04 Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals

Publications (1)

Publication Number Publication Date
ATE552557T1 true ATE552557T1 (de) 2012-04-15

Family

ID=40674058

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09717759T ATE552557T1 (de) 2008-02-29 2009-02-04 Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale

Country Status (7)

Country Link
US (2) US7804735B2 (de)
EP (1) EP2263153B1 (de)
JP (1) JP5474837B2 (de)
KR (1) KR101108342B1 (de)
CN (2) CN101960436B (de)
AT (1) ATE552557T1 (de)
WO (1) WO2009111125A1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US9710384B2 (en) 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US7804735B2 (en) * 2008-02-29 2010-09-28 Qualcomm Incorporated Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals
TW201026070A (en) * 2008-12-29 2010-07-01 Sunplus Technology Co Ltd Apparatus and method for accessing data
US8589714B2 (en) * 2009-12-18 2013-11-19 Texas Instruments Incorporated Falling clock edge JTAG bus routers
WO2011106049A1 (en) * 2010-02-23 2011-09-01 Rambus Inc. Time multiplexing at different rates to access different memory types
US8595402B1 (en) * 2010-03-02 2013-11-26 Marvell International Ltd. Dynamic arbitration schemes for multi-master memory systems
JP5471631B2 (ja) * 2010-03-10 2014-04-16 セイコーエプソン株式会社 電子機器
US8472279B2 (en) 2010-08-31 2013-06-25 Micron Technology, Inc. Channel skewing
KR101854251B1 (ko) * 2010-11-30 2018-05-03 삼성전자주식회사 멀티 채널 반도체 메모리 장치 및 그를 구비하는 반도체 장치
US20130111122A1 (en) * 2011-10-31 2013-05-02 Futurewei Technologies, Inc. Method and apparatus for network table lookups
CN103129185B (zh) * 2011-12-05 2016-04-06 珠海天威技术开发有限公司 数据存储装置及其数据访问方法、成像设备
US10355001B2 (en) * 2012-02-15 2019-07-16 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
US9348775B2 (en) 2012-03-16 2016-05-24 Analog Devices, Inc. Out-of-order execution of bus transactions
US9323608B2 (en) 2012-06-07 2016-04-26 Micron Technology, Inc. Integrity of a data bus
US9009570B2 (en) 2012-06-07 2015-04-14 Micron Technology, Inc. Integrity of an address bus
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
TWI498812B (zh) * 2013-01-07 2015-09-01 Mstar Semiconductor Inc 資料存取方法以及使用此資料存取方法的電子裝置
CN103970479B (zh) * 2013-01-24 2018-05-22 晨星半导体股份有限公司 数据存取方法以及使用此数据存取方法的电子装置
US9811455B2 (en) * 2013-03-15 2017-11-07 The Boeing Company Accessing different types of memory by respective distinct command with different timing requirements
US9111607B2 (en) * 2013-05-31 2015-08-18 Freescale Semiconductor, Inc. Multiple data rate memory with read timing information
KR102149768B1 (ko) 2014-04-29 2020-08-31 삼성전자주식회사 불휘발성 메모리 시스템
JP6434870B2 (ja) 2015-07-28 2018-12-05 ルネサスエレクトロニクス株式会社 電子装置
JP6348234B2 (ja) * 2015-09-18 2018-06-27 株式会社日立製作所 メモリコントローラ、メモリ制御方法および半導体記憶装置
WO2017127634A1 (en) * 2016-01-22 2017-07-27 Sony Interactive Entertainment Inc Simulating legacy bus behavior for backwards compatibility
CN105760310B (zh) * 2016-02-05 2018-12-14 华为技术有限公司 地址分配方法及ddr控制器
US10380060B2 (en) * 2016-06-17 2019-08-13 Etron Technology, Inc. Low-pincount high-bandwidth memory and memory bus
US9773543B1 (en) * 2016-08-31 2017-09-26 Xilinx, Inc. Effective clamshell mirroring for memory interfaces
US9940984B1 (en) * 2016-09-28 2018-04-10 Intel Corporation Shared command address (C/A) bus for multiple memory channels
US10846018B2 (en) * 2017-04-05 2020-11-24 Mediatek Inc. Memory device, memory controller and associated memory system operated according to selected clock signals
KR20180113371A (ko) * 2017-04-06 2018-10-16 에스케이하이닉스 주식회사 데이터 저장 장치
US10541020B2 (en) * 2018-02-27 2020-01-21 Seagate Technology Llc Controller architecture for reducing on-die capacitance
WO2019169586A1 (en) * 2018-03-07 2019-09-12 Micron Technology, Inc. Performing read operation prior to two-pass programming of storage system
US10635357B2 (en) 2018-07-03 2020-04-28 Nvidia Corporation Method for overlapping memory accesses
US11048654B2 (en) * 2018-10-24 2021-06-29 Innogrit Technologies Co., Ltd. Systems and methods for providing multiple memory channels with one set of shared address pins on the physical interface
TWI692759B (zh) * 2019-05-15 2020-05-01 瑞昱半導體股份有限公司 同時存取第一動態隨機存取記憶體與第二動態隨機存取記憶體的方法及相關的記憶體控制器
US10936234B2 (en) * 2019-05-22 2021-03-02 Macronix International Co., Ltd. Data transfer between memory devices on shared bus
CN112286842B (zh) * 2019-07-22 2023-07-04 苏州库瀚信息科技有限公司 用于存储器控制器与存储器设备互连的总线
US11409684B2 (en) * 2020-07-31 2022-08-09 Alibaba Group Holding Limited Processing accelerator architectures
US11360897B1 (en) * 2021-04-15 2022-06-14 Qualcomm Incorporated Adaptive memory access management
KR20240117196A (ko) * 2023-01-25 2024-08-01 삼성전자주식회사 클럭 드라이버, 이의 동작 방법, 클럭 드라이버를 포함하는 메모리 장치, 및 메모리 시스템

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100306881B1 (ko) 1998-04-02 2001-10-29 박종섭 동기 반도체 메모리를 위한 인터페이스
JP2000285016A (ja) 1999-03-30 2000-10-13 Sanyo Electric Co Ltd メモリ制御回路
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
JP4074110B2 (ja) 2002-03-20 2008-04-09 Ｎｅｃエレクトロニクス株式会社 シングルチップ・マイクロコンピュータ
US7003684B2 (en) 2002-03-27 2006-02-21 Via Technologies, Inc. Memory control chip, control method and control circuit
US7023719B1 (en) * 2003-10-23 2006-04-04 Lsi Logic Corporation Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board
WO2005083572A1 (ja) 2004-03-02 2005-09-09 Sony Corporation メモリ制御装置、メモリ制御方法、メモリ制御プログラムおよび画像撮像装置
JP3829851B2 (ja) * 2004-03-09 2006-10-04 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US20060036826A1 (en) 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
WO2008041963A2 (en) * 2005-07-27 2008-04-10 The Board Of Trustees Of The University Of Illinois Bi-direction rapid action electrostatically actuated microvalve
US7177230B1 (en) * 2005-08-25 2007-02-13 Mediatek Inc. Memory controller and memory system
US7804735B2 (en) 2008-02-29 2010-09-28 Qualcomm Incorporated Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals

Also Published As

Publication number Publication date
EP2263153B1 (de) 2012-04-04
JP5474837B2 (ja) 2014-04-16
CN103279438B (zh) 2016-01-20
US7804735B2 (en) 2010-09-28
CN103279438A (zh) 2013-09-04
EP2263153A1 (de) 2010-12-22
CN101960436B (zh) 2013-07-17
KR101108342B1 (ko) 2012-01-25
KR20100117687A (ko) 2010-11-03
CN101960436A (zh) 2011-01-26
JP2011513845A (ja) 2011-04-28
US20090219779A1 (en) 2009-09-03
US20100318730A1 (en) 2010-12-16
US8325525B2 (en) 2012-12-04
WO2009111125A1 (en) 2009-09-11

Similar Documents

Publication Publication Date Title
ATE552557T1 (de) Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale
NZ597129A (en) Hmo synthesis
WO2012166535A3 (en) Apparatus including memory system controllers and related methods
WO2012009103A3 (en) Method and apparatus for training a memory signal via an error signal of a memory
WO2012170954A3 (en) Line based image processing and flexible memory system
GB2472952A (en) Dynamic pass voltage
TW200730861A (en) Method and apparatus for acoustic system having a transceiver module
WO2011016934A3 (en) Method and system for synchronizing address and control signals in threaded memory modules
GB2520175A (en) Apparatus and methods for multi-mode asynchronous communication
EP3038086A3 (de) Steuerungsquellentreiber-ic, anzeigevorrichtung und signalübertragungsverfahren dafür
TW200737064A (en) Display control system of a display device and control method thereof
EP2179363A4 (de) System und verfahren zum starten eines speichersystems sowie speichervorrichtung und system auf prozessorbasis damit
MX2012003331A (es) Datos de entretenimiento de cara compartidos.
WO2012166548A3 (en) Apparatus including memory system controllers and related methods
EP3301669A3 (de) Anzeigevorrichtung und verfahren zum sub-pixel-übergang
TW200734743A (en) Method of transmitting data signals and control signals using a signal data bus and related apparatus
GB201001551D0 (en) Display system for simultaneous displaying of windows generated by multiple window systems belonging to the same computer platform
IN2014CN03944A (de)
EP2166530A3 (de) Flüssigkristallanzeige und Anzeigesystem damit
ATE555461T1 (de) Verfahren und system zum transfer von informationen
MX342875B (es) Metodos y aparatos para obtener señales compensadas para determinar los parametros de una formacion.
WO2013002868A3 (en) Circuits and methods for memory
MY179336A (en) Device, method and system for performing closed chassis debug with a repeater
ATE512525T1 (de) Verfahren zum übertragen von feldbus-daten sowie feldbus-kommunikationssystem
ATE511676T1 (de) Scheduling auf der basis eines turnaround- ereignisses