ATE556503T1 - Taktrückgewinnungsvorrichtung und elektronische ausrüstung - Google Patents

Taktrückgewinnungsvorrichtung und elektronische ausrüstung

Info

Publication number
ATE556503T1
ATE556503T1 AT10004754T AT10004754T ATE556503T1 AT E556503 T1 ATE556503 T1 AT E556503T1 AT 10004754 T AT10004754 T AT 10004754T AT 10004754 T AT10004754 T AT 10004754T AT E556503 T1 ATE556503 T1 AT E556503T1
Authority
AT
Austria
Prior art keywords
gating
nth
signal
groups
section adapted
Prior art date
Application number
AT10004754T
Other languages
English (en)
Inventor
Kenichi Maruko
Hiroki Kihara
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of ATE556503T1 publication Critical patent/ATE556503T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
AT10004754T 2009-06-02 2010-05-05 Taktrückgewinnungsvorrichtung und elektronische ausrüstung ATE556503T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009133238A JP5397025B2 (ja) 2009-06-02 2009-06-02 クロック再生装置および電子機器

Publications (1)

Publication Number Publication Date
ATE556503T1 true ATE556503T1 (de) 2012-05-15

Family

ID=42456390

Family Applications (1)

Application Number Title Priority Date Filing Date
AT10004754T ATE556503T1 (de) 2009-06-02 2010-05-05 Taktrückgewinnungsvorrichtung und elektronische ausrüstung

Country Status (5)

Country Link
US (1) US8125278B2 (de)
EP (1) EP2259486B1 (de)
JP (1) JP5397025B2 (de)
CN (1) CN101908884B (de)
AT (1) ATE556503T1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8847691B2 (en) 2011-11-16 2014-09-30 Qualcomm Incorporated Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data
TWI451700B (zh) * 2011-12-05 2014-09-01 Global Unichip Corp 時脈資料回復電路
US20130216003A1 (en) * 2012-02-16 2013-08-22 Qualcomm Incorporated RESETTABLE VOLTAGE CONTROLLED OSCILLATORS (VCOs) FOR CLOCK AND DATA RECOVERY (CDR) CIRCUITS, AND RELATED SYSTEMS AND METHODS
RU2517269C2 (ru) * 2012-03-20 2014-05-27 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Устройство тактовой синхронизации для преобразования прерывистой информации в непрерывную
JP6032082B2 (ja) * 2013-03-25 2016-11-24 富士通株式会社 受信回路及び半導体集積回路
JP6159221B2 (ja) * 2013-10-17 2017-07-05 株式会社東芝 Ｃｄｒ回路、および、シリアル通信インターフェイス回路
CN103901262A (zh) * 2014-04-11 2014-07-02 北京理工大学 一种纳秒级脉冲峰值检测方法
US9337817B2 (en) * 2014-06-17 2016-05-10 Via Alliance Semiconductor Co., Ltd. Hold-time optimization circuit and receiver with the same
KR102491690B1 (ko) * 2016-08-17 2023-01-26 에스케이하이닉스 주식회사 클락 검출기 및 클락 검출 방법
CN108616270B (zh) * 2018-05-16 2021-10-15 珠海市杰理科技股份有限公司 恢复电路和接收设备
CN110426974B (zh) * 2019-08-08 2024-04-09 南京邮电大学 一种基于正交相位选通的等效采样控制电路
CN112799465B (zh) * 2019-10-28 2024-08-06 京东方科技集团股份有限公司 控制信号发生器及其驱动方法
JP7375655B2 (ja) * 2020-03-31 2023-11-08 株式会社デンソー パルスエッジ検出回路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237290A (en) * 1992-05-08 1993-08-17 At&T Bell Laboratories Method and apparatus for clock recovery
JP3346442B2 (ja) * 1995-02-07 2002-11-18 日本電信電話株式会社 タイミング抽出回路
JPH10215288A (ja) * 1997-01-29 1998-08-11 Hitachi Ltd 非接触ｉｃカード
JP3209943B2 (ja) * 1997-06-13 2001-09-17 沖電気工業株式会社 電圧制御遅延回路、直接位相制御型電圧制御発振器、クロック／データ再生回路及びクロック／データ再生装置
JP3019814B2 (ja) * 1997-09-18 2000-03-13 日本電気株式会社 クロックリカバリ回路
US6259326B1 (en) * 1999-08-24 2001-07-10 Agere Systems Guardian Corp. Clock recovery from a burst-mode digital signal each packet of which may have one of several predefined frequencies
JP3394013B2 (ja) * 1999-12-24 2003-04-07 松下電器産業株式会社 データ抽出回路およびデータ抽出システム
JP2002135114A (ja) * 2000-10-24 2002-05-10 Sony Corp 位相同期回路およびこれを用いた発振装置
JP3725869B2 (ja) * 2001-02-27 2005-12-14 ティーオーエー株式会社 クロック再生回路
JP4031671B2 (ja) * 2002-06-11 2008-01-09 松下電器産業株式会社 クロックリカバリ回路
JP4158465B2 (ja) * 2002-09-10 2008-10-01 日本電気株式会社 クロック再生装置、および、クロック再生装置を用いた電子機器
US7983370B2 (en) * 2003-12-08 2011-07-19 Nec Corporation Clock and data recovery circuit
US7667544B2 (en) * 2006-01-12 2010-02-23 Yokogawa Electric Corporation Clock reproducing apparatus
JP4731511B2 (ja) * 2007-03-12 2011-07-27 日本電信電話株式会社 クロック・データ再生方法および回路

Also Published As

Publication number Publication date
JP2010283455A (ja) 2010-12-16
EP2259486B1 (de) 2012-05-02
EP2259486A3 (de) 2011-01-26
CN101908884A (zh) 2010-12-08
US20100301950A1 (en) 2010-12-02
CN101908884B (zh) 2013-03-06
US8125278B2 (en) 2012-02-28
JP5397025B2 (ja) 2014-01-22
EP2259486A2 (de) 2010-12-08

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