ATE73566T1 - MULTI-PORT MEMORY AND SOURCE DEVICE FOR IMAGE POINT INFORMATION. - Google Patents
MULTI-PORT MEMORY AND SOURCE DEVICE FOR IMAGE POINT INFORMATION.Info
- Publication number
- ATE73566T1 ATE73566T1 AT86400976T AT86400976T ATE73566T1 AT E73566 T1 ATE73566 T1 AT E73566T1 AT 86400976 T AT86400976 T AT 86400976T AT 86400976 T AT86400976 T AT 86400976T AT E73566 T1 ATE73566 T1 AT E73566T1
- Authority
- AT
- Austria
- Prior art keywords
- mask means
- shift registers
- bit map
- bidirectional
- map memory
- Prior art date
Links
- 230000002457 bidirectional effect Effects 0.000 abstract 5
- 230000005540 biological transmission Effects 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
- G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Image Input (AREA)
- Controls And Circuits For Display Device (AREA)
- Digital Computer Display Output (AREA)
Abstract
The present system includes, in a preferred embodiment, a plurality of bit map memory units which together define a large bit map memory. For each bit map memory unit there is also included a mask means and four extended shift registers. The shift registers can be loaded in parallel with pixel information through bidirectional data transmission channels which include bidirectional mask means. The pixel information can be routed through said bidirectional mask means to different address locations, or to the same address location, with certain of the pixel bits removed by the mask means. The shift registers have both serial and parallel input and output mans and are clocked at different speeds to accommodate different peripherals. At least a first shift register is designed to be serially read out at a relatively high rate which can be advantageously used by a video display device or the like. Information signals from the other shift registers are transferred at high speed (in parallel) into and out of the large bit map memory to said first shift register whereby pixel information signals are settled down before being routed from said first shift register. The bidirectional mask means and the bidirectional data transmission channels along with the multiplicity of shift registers permit the present system to handle many varied operations which operate at different speeds.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP86400976A EP0245564B1 (en) | 1986-05-06 | 1986-05-06 | A multiport memory and source arrangement for pixel information |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE73566T1 true ATE73566T1 (en) | 1992-03-15 |
Family
ID=8196299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT86400976T ATE73566T1 (en) | 1986-05-06 | 1986-05-06 | MULTI-PORT MEMORY AND SOURCE DEVICE FOR IMAGE POINT INFORMATION. |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0245564B1 (en) |
| AT (1) | ATE73566T1 (en) |
| DE (1) | DE3684309D1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4953101A (en) * | 1987-11-24 | 1990-08-28 | Digital Equipment Corporation | Software configurable memory architecture for data processing system having graphics capability |
| NL8801116A (en) * | 1988-04-29 | 1989-11-16 | Oce Nederland Bv | METHOD AND APPARATUS FOR CONVERTING CONFIRMATION DATA TO GRID DATA |
| DE69025439T2 (en) * | 1989-07-28 | 1996-07-18 | Texas Instruments Inc | Graphic display system with a divided serial register |
| JPH07501164A (en) * | 1991-11-21 | 1995-02-02 | イマジネイション テクノロジーズ リミテッド | Video/graphics memory system |
| US5473566A (en) * | 1994-09-12 | 1995-12-05 | Cirrus Logic, Inc. | Memory architecture and devices, systems and methods utilizing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4174536A (en) * | 1977-01-21 | 1979-11-13 | Massachusetts Institute Of Technology | Digital communications controller with firmware control |
| US4546451A (en) * | 1982-02-12 | 1985-10-08 | Metheus Corporation | Raster graphics display refresh memory architecture offering rapid access speed |
| JPS59180871A (en) * | 1983-03-31 | 1984-10-15 | Fujitsu Ltd | Semiconductor memory device |
-
1986
- 1986-05-06 EP EP86400976A patent/EP0245564B1/en not_active Expired
- 1986-05-06 AT AT86400976T patent/ATE73566T1/en not_active IP Right Cessation
- 1986-05-06 DE DE8686400976T patent/DE3684309D1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3684309D1 (en) | 1992-04-16 |
| EP0245564A1 (en) | 1987-11-19 |
| EP0245564B1 (en) | 1992-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| UEP | Publication of translation of european patent specification | ||
| REN | Ceased due to non-payment of the annual fee |