ATE73566T1 - Multi-port-speicher und quelleneinrichtung fuer bildpunktinformation. - Google Patents

Multi-port-speicher und quelleneinrichtung fuer bildpunktinformation.

Info

Publication number
ATE73566T1
ATE73566T1 AT86400976T AT86400976T ATE73566T1 AT E73566 T1 ATE73566 T1 AT E73566T1 AT 86400976 T AT86400976 T AT 86400976T AT 86400976 T AT86400976 T AT 86400976T AT E73566 T1 ATE73566 T1 AT E73566T1
Authority
AT
Austria
Prior art keywords
mask means
shift registers
bit map
bidirectional
map memory
Prior art date
Application number
AT86400976T
Other languages
English (en)
Inventor
Thomas C Stockebrand
Joel D Kaufman
Earle R Vickery Iii
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE73566T1 publication Critical patent/ATE73566T1/de

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Digital Computer Display Output (AREA)
AT86400976T 1986-05-06 1986-05-06 Multi-port-speicher und quelleneinrichtung fuer bildpunktinformation. ATE73566T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86400976A EP0245564B1 (de) 1986-05-06 1986-05-06 Multi-Port-Speicher und Quelleneinrichtung für Bildpunktinformation

Publications (1)

Publication Number Publication Date
ATE73566T1 true ATE73566T1 (de) 1992-03-15

Family

ID=8196299

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86400976T ATE73566T1 (de) 1986-05-06 1986-05-06 Multi-port-speicher und quelleneinrichtung fuer bildpunktinformation.

Country Status (3)

Country Link
EP (1) EP0245564B1 (de)
AT (1) ATE73566T1 (de)
DE (1) DE3684309D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953101A (en) * 1987-11-24 1990-08-28 Digital Equipment Corporation Software configurable memory architecture for data processing system having graphics capability
NL8801116A (nl) * 1988-04-29 1989-11-16 Oce Nederland Bv Werkwijze en inrichting voor het converteren van omtrekgegevens naar rastergegevens.
DE69025439T2 (de) * 1989-07-28 1996-07-18 Texas Instruments Inc Graphisches Anzeigesystem mit einem geteilten seriellen Register
JPH07501164A (ja) * 1991-11-21 1995-02-02 イマジネイション テクノロジーズ リミテッド ビデオ／グラフィックメモリシステム
US5473566A (en) * 1994-09-12 1995-12-05 Cirrus Logic, Inc. Memory architecture and devices, systems and methods utilizing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4174536A (en) * 1977-01-21 1979-11-13 Massachusetts Institute Of Technology Digital communications controller with firmware control
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
JPS59180871A (ja) * 1983-03-31 1984-10-15 Fujitsu Ltd 半導体メモリ装置

Also Published As

Publication number Publication date
EP0245564A1 (de) 1987-11-19
DE3684309D1 (de) 1992-04-16
EP0245564B1 (de) 1992-03-11

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee