ATE73578T1 - Verfahren zur herstellung von graeben in integrierten schaltungen. - Google Patents

Verfahren zur herstellung von graeben in integrierten schaltungen.

Info

Publication number
ATE73578T1
ATE73578T1 AT85307999T AT85307999T ATE73578T1 AT E73578 T1 ATE73578 T1 AT E73578T1 AT 85307999 T AT85307999 T AT 85307999T AT 85307999 T AT85307999 T AT 85307999T AT E73578 T1 ATE73578 T1 AT E73578T1
Authority
AT
Austria
Prior art keywords
trench
silicon
voids
layer
integrated circuit
Prior art date
Application number
AT85307999T
Other languages
English (en)
Inventor
William L Price
Ronald L Schlupp
Mammen Thomas
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE73578T1 publication Critical patent/ATE73578T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT85307999T 1984-11-05 1985-11-04 Verfahren zur herstellung von graeben in integrierten schaltungen. ATE73578T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/668,225 US4639288A (en) 1984-11-05 1984-11-05 Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching
EP85307999A EP0181188B1 (de) 1984-11-05 1985-11-04 Verfahren zur Herstellung von Gräben in integrierten Schaltungen

Publications (1)

Publication Number Publication Date
ATE73578T1 true ATE73578T1 (de) 1992-03-15

Family

ID=24681482

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85307999T ATE73578T1 (de) 1984-11-05 1985-11-04 Verfahren zur herstellung von graeben in integrierten schaltungen.

Country Status (5)

Country Link
US (1) US4639288A (de)
EP (1) EP0181188B1 (de)
JP (1) JPS61115336A (de)
AT (1) ATE73578T1 (de)
DE (1) DE3585592D1 (de)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5082795A (en) * 1986-12-05 1992-01-21 General Electric Company Method of fabricating a field effect semiconductor device having a self-aligned structure
JPS6430248A (en) * 1987-07-27 1989-02-01 Hitachi Ltd Formation of on-the-trench insulation film
JPS6432633A (en) * 1987-07-29 1989-02-02 Hitachi Ltd Taper etching method
JPH01134914A (ja) * 1987-11-20 1989-05-26 Fujitsu Ltd 半導体装置の製造方法
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate
US4853344A (en) * 1988-08-12 1989-08-01 Advanced Micro Devices, Inc. Method of integrated circuit isolation oxidizing walls of isolation slot, growing expitaxial layer over isolation slot, and oxidizing epitaxial layer over isolation slot
JPH03129854A (ja) * 1989-10-16 1991-06-03 Toshiba Corp 半導体装置の製造方法
US5188704A (en) * 1989-10-20 1993-02-23 International Business Machines Corporation Selective silicon nitride plasma etching
KR960006714B1 (ko) * 1990-05-28 1996-05-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법
DE4037202A1 (de) * 1990-11-22 1992-05-27 Asea Brown Boveri Verfahren zum herstellen von graeben in einem einkristallinen siliziumkoerper
US5431772A (en) * 1991-05-09 1995-07-11 International Business Machines Corporation Selective silicon nitride plasma etching process
US5302239A (en) * 1992-05-15 1994-04-12 Micron Technology, Inc. Method of making atomically sharp tips useful in scanning probe microscopes
US5753130A (en) 1992-05-15 1998-05-19 Micron Technology, Inc. Method for forming a substantially uniform array of sharp tips
US5302238A (en) * 1992-05-15 1994-04-12 Micron Technology, Inc. Plasma dry etch to produce atomically sharp asperities useful as cold cathodes
US5516720A (en) * 1994-02-14 1996-05-14 United Microelectronics Corporation Stress relaxation in dielectric before metallization
US5508234A (en) * 1994-10-31 1996-04-16 International Business Machines Corporation Microcavity structures, fabrication processes, and applications thereof
DE69533773D1 (de) * 1995-03-31 2004-12-23 Cons Ric Microelettronica Verfahren zur Herstellung von Isolationsgraben
JP3360970B2 (ja) * 1995-05-22 2003-01-07 株式会社東芝 半導体装置の製造方法
US6579777B1 (en) * 1996-01-16 2003-06-17 Cypress Semiconductor Corp. Method of forming local oxidation with sloped silicon recess
US5872392A (en) * 1996-04-30 1999-02-16 Nippon Steel Corporation Semiconductor device and a method of fabricating the same
US5710079A (en) * 1996-05-24 1998-01-20 Lsi Logic Corporation Method and apparatus for forming dielectric films
US5882982A (en) * 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US6555484B1 (en) 1997-06-19 2003-04-29 Cypress Semiconductor Corp. Method for controlling the oxidation of implanted silicon
US6008131A (en) * 1997-12-22 1999-12-28 Taiwan Semiconductor Manufacturing Company Ltd. Bottom rounding in shallow trench etching using a highly isotropic etching step
US5994229A (en) * 1998-01-12 1999-11-30 Taiwan Semiconductor Manufacturing Company Ltd. Achievement of top rounding in shallow trench etch
US6333274B2 (en) * 1998-03-31 2001-12-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device including a seamless shallow trench isolation step
US6096659A (en) * 1998-04-13 2000-08-01 Advanced Micro Devices, Inc. Manufacturing process for reducing feature dimensions in a semiconductor
US6175147B1 (en) * 1998-05-14 2001-01-16 Micron Technology Inc. Device isolation for semiconductor devices
US6165905A (en) * 1999-01-20 2000-12-26 Philips Electronics, North America Corp. Methods for making reliable via structures having hydrophobic inner wall surfaces
KR100559033B1 (ko) * 1999-12-24 2006-03-10 주식회사 하이닉스반도체 반도체 소자의 쉘로우 트렌치 소자분리막 형성 방법
US6727158B2 (en) * 2001-11-08 2004-04-27 Micron Technology, Inc. Structure and method for forming a faceted opening and a layer filling therein
US6727150B2 (en) * 2002-07-26 2004-04-27 Micron Technology, Inc. Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers
DE10318568A1 (de) * 2003-04-15 2004-11-25 Technische Universität Dresden Siliziumsubstrat mit positiven Ätzprofilen mit definiertem Böschungswinkel und Verfahren zur Herstellung
DE10342559B3 (de) * 2003-09-15 2005-04-14 Infineon Technologies Ag Randstruktur eines Leistungshalbleiterbauelementes und ihr Herstellungsverfahren
US7122416B2 (en) * 2003-10-31 2006-10-17 Analog Devices, Inc. Method for forming a filled trench in a semiconductor layer of a semiconductor substrate, and a semiconductor substrate with a semiconductor layer having a filled trench therein
KR100567624B1 (ko) * 2004-06-15 2006-04-04 삼성전자주식회사 반도체 장치의 제조 방법
JP4379475B2 (ja) * 2004-12-24 2009-12-09 株式会社村田製作所 圧電薄膜共振子およびその製造方法
US20070235783A9 (en) * 2005-07-19 2007-10-11 Micron Technology, Inc. Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
US7772672B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Semiconductor constructions
US20070212874A1 (en) * 2006-03-08 2007-09-13 Micron Technology, Inc. Method for filling shallow isolation trenches and other recesses during the formation of a semiconductor device and electronic systems including the semiconductor device
US7799694B2 (en) 2006-04-11 2010-09-21 Micron Technology, Inc. Methods of forming semiconductor constructions
KR100945227B1 (ko) * 2006-09-28 2010-03-03 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 형성방법
KR101169167B1 (ko) * 2010-10-25 2012-07-30 에스케이하이닉스 주식회사 반도체 소자 및 그 형성 방법
US8546234B2 (en) * 2011-06-06 2013-10-01 Nanya Technology Corporation Semiconductor process
WO2013047807A1 (ja) * 2011-09-30 2013-04-04 株式会社大真空 電子部品パッケージ、電子部品パッケージ用封止部材、および前記電子部品パッケージ用封止部材の製造方法
EP3618103A1 (de) * 2018-08-30 2020-03-04 IMEC vzw Strukturierungsmethode

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577936A (en) * 1980-06-18 1982-01-16 Fujitsu Ltd Manufacture of semiconductor device
DE3174468D1 (en) * 1980-09-17 1986-05-28 Hitachi Ltd Semiconductor device and method of manufacturing the same
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US4403396A (en) * 1981-12-24 1983-09-13 Gte Laboratories Incorporated Semiconductor device design and process
JPS59149030A (ja) * 1983-02-16 1984-08-25 Hitachi Ltd 半導体装置の製造法

Also Published As

Publication number Publication date
EP0181188A2 (de) 1986-05-14
EP0181188A3 (en) 1988-09-28
US4639288A (en) 1987-01-27
JPS61115336A (ja) 1986-06-02
EP0181188B1 (de) 1992-03-11
DE3585592D1 (de) 1992-04-16

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