ATE77888T1 - Binaere subtrahierschaltung. - Google Patents

Binaere subtrahierschaltung.

Info

Publication number
ATE77888T1
ATE77888T1 AT85308965T AT85308965T ATE77888T1 AT E77888 T1 ATE77888 T1 AT E77888T1 AT 85308965 T AT85308965 T AT 85308965T AT 85308965 T AT85308965 T AT 85308965T AT E77888 T1 ATE77888 T1 AT E77888T1
Authority
AT
Austria
Prior art keywords
exclusive
gate
output
borrow
input
Prior art date
Application number
AT85308965T
Other languages
English (en)
Inventor
John Armer
Original Assignee
Rca Thomson Licensing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Thomson Licensing Corp filed Critical Rca Thomson Licensing Corp
Application granted granted Critical
Publication of ATE77888T1 publication Critical patent/ATE77888T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Networks Using Active Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Details Of Television Scanning (AREA)
  • Testing Of Coins (AREA)
  • Processing Of Color Television Signals (AREA)
  • Credit Cards Or The Like (AREA)
  • Magnetic Record Carriers (AREA)
  • Holo Graphy (AREA)
  • Switches That Are Operated By Magnetic Or Electric Fields (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Electronic Switches (AREA)
AT85308965T 1984-12-14 1985-12-10 Binaere subtrahierschaltung. ATE77888T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/682,014 US4685079A (en) 1984-12-14 1984-12-14 Ripple-borrow binary subtraction circuit
EP85308965A EP0185504B1 (de) 1984-12-14 1985-12-10 Binäre Subtrahierschaltung

Publications (1)

Publication Number Publication Date
ATE77888T1 true ATE77888T1 (de) 1992-07-15

Family

ID=24737826

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85308965T ATE77888T1 (de) 1984-12-14 1985-12-10 Binaere subtrahierschaltung.

Country Status (10)

Country Link
US (1) US4685079A (de)
EP (1) EP0185504B1 (de)
JP (1) JPH0746312B2 (de)
KR (1) KR940004325B1 (de)
AT (1) ATE77888T1 (de)
AU (1) AU576408B2 (de)
CA (1) CA1252897A (de)
DE (1) DE3586283T2 (de)
ES (1) ES8705130A1 (de)
HK (1) HK88497A (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4709346A (en) * 1985-04-01 1987-11-24 Raytheon Company CMOS subtractor
JPS62103732A (ja) * 1985-10-30 1987-05-14 Mitsubishi Electric Corp Ｍｏｓトランジスタ回路
GB8531380D0 (en) * 1985-12-20 1986-02-05 Texas Instruments Ltd Multi-stage parallel binary adder
JPH087672B2 (ja) * 1986-04-04 1996-01-29 松下電器産業株式会社 減算セル
US4739503A (en) * 1986-04-21 1988-04-19 Rca Corporation Carry/borrow propagate adder/subtractor
JPH0810427B2 (ja) * 1986-11-07 1996-01-31 松下電器産業株式会社 減算セル
FR2612660B1 (fr) * 1987-03-18 1990-10-19 Hmida Hedi Dispositif de calcul binaire
IT1210751B (it) * 1987-05-20 1989-09-20 Cselt Centro Studi Lab Telecom Sommatore veloce in tecnologia c mos
EP0309348B1 (de) * 1987-09-23 1993-04-21 France Telecom Binäre Additions- und Multiplikationsvorrichtung
JP2563467B2 (ja) * 1988-04-20 1996-12-11 富士通株式会社 ２進演算器
US4935719A (en) * 1989-03-31 1990-06-19 Sgs-Thomson Microelectronics, Inc. Comparator circuitry
US7073720B2 (en) 1994-06-22 2006-07-11 Scientific Gaines International, Inc. Lottery ticket bar code
KR100255962B1 (ko) * 1995-11-03 2000-05-01 윤종용 3-상태회로의 출력 안정화회로
US6018757A (en) * 1996-08-08 2000-01-25 Samsung Electronics Company, Ltd. Zero detect for binary difference
EP1271303A1 (de) * 2001-06-22 2003-01-02 STMicroelectronics S.r.l. Binärzahlvergleicher
US8707225B1 (en) * 2006-04-07 2014-04-22 Cadence Design Systems, Inc. Synthesis of area-efficient subtractor and divider functional blocks
US7991820B1 (en) 2007-08-07 2011-08-02 Leslie Imre Sohay One step binary summarizer
JP2009301210A (ja) * 2008-06-11 2009-12-24 Tokyo Denki Univ Ｎ桁減算器ユニット、ｎ桁減算器モジュール、ｎ桁加算器ユニット及びｎ桁加算器モジュール
RU2621375C1 (ru) * 2015-12-08 2017-06-02 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" Двоичный вычитатель
KR102923380B1 (ko) 2020-06-10 2026-02-05 에스케이하이닉스 주식회사 연산 회로

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
US4052604A (en) * 1976-01-19 1977-10-04 Hewlett-Packard Company Binary adder
US4152775A (en) * 1977-07-20 1979-05-01 Intel Corporation Single line propagation adder and method for binary addition
JPS54127645A (en) * 1978-03-28 1979-10-03 Fujitsu Ltd Full subtractor using josephson logic gate
US4357675A (en) * 1980-08-04 1982-11-02 Bell Telephone Laboratories, Incorporated Ripple-carry generating circuit with carry regeneration
US4439835A (en) * 1981-07-14 1984-03-27 Rockwell International Corporation Apparatus for and method of generation of ripple carry signals in conjunction with logical adding circuitry
US4425623A (en) * 1981-07-14 1984-01-10 Rockwell International Corporation Lookahead carry circuit apparatus
US4471454A (en) * 1981-10-27 1984-09-11 Ibm Corporation Fast, efficient, small adder
US4523292A (en) * 1982-09-30 1985-06-11 Rca Corporation Complementary FET ripple carry binary adder circuit
JPS5999541A (ja) * 1982-11-29 1984-06-08 Nec Corp 算術論理演算回路
JPS59139447A (ja) * 1983-01-28 1984-08-10 Matsushita Electric Ind Co Ltd 全加算器

Also Published As

Publication number Publication date
DE3586283D1 (de) 1992-08-06
JPH0746312B2 (ja) 1995-05-17
KR860005285A (ko) 1986-07-21
EP0185504B1 (de) 1992-07-01
KR940004325B1 (ko) 1994-05-19
EP0185504A3 (en) 1988-06-15
AU5086585A (en) 1986-06-19
US4685079A (en) 1987-08-04
ES549655A0 (es) 1987-04-16
ES8705130A1 (es) 1987-04-16
DE3586283T2 (de) 1992-12-10
HK88497A (en) 1997-06-27
CA1252897A (en) 1989-04-18
EP0185504A2 (de) 1986-06-25
AU576408B2 (en) 1988-08-25
JPS61143842A (ja) 1986-07-01

Similar Documents

Publication Publication Date Title
ATE77888T1 (de) Binaere subtrahierschaltung.
JPS6471217A (en) Output buffer circuit
KR890004212B1 (en) Complementary logic circuit
GB1364281A (en) Binary full addersubstractors
KR890005996A (ko) 동기 플립플롭회로
GB1370714A (en) Integrated bistable circuit
GB1036902A (en) Improvements relating to digital subtracting apparatus
GB1290057A (de)
JPS55656A (en) Complementary mos logic circuit
JPS57197910A (en) Comparator circuit
SU1182665A1 (ru) Элемент с трем состо ни ми
JPS57157639A (en) Semiconductor circuit
ES385332A1 (es) Puerta logica.
KR890004467B1 (en) Semiconductor latch circuit with noise resistance circuit
GB1060836A (en) Improvements in or relating to electrical circuits
JPS57176516A (en) Pcm signal device
SU1492452A1 (ru) Триггер со счетным входом на взаимодополн ющих МДП-транзисторах
KR900003725A (ko) 테스트 모우드 기능 수행 입력 회로
JPS56126316A (en) Mos comparing integrated circuit
KR830008614A (ko) 매트릭스(matrix) 회로
JPS56105539A (en) Adder of pcm signal
KR890010690A (ko) 전 가산기를 이용한 승수회로
GB922106A (en) Binary adding circuit
JPS57178543A (en) Digital comparator
GB1241618A (en) An electronic logic network

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee