ATE85861T1 - Niederleistungsadressenpuffer mit aktiver wirkung. - Google Patents

Niederleistungsadressenpuffer mit aktiver wirkung.

Info

Publication number
ATE85861T1
ATE85861T1 AT86401319T AT86401319T ATE85861T1 AT E85861 T1 ATE85861 T1 AT E85861T1 AT 86401319 T AT86401319 T AT 86401319T AT 86401319 T AT86401319 T AT 86401319T AT E85861 T1 ATE85861 T1 AT E85861T1
Authority
AT
Austria
Prior art keywords
low
address buffer
active effect
performance address
performance
Prior art date
Application number
AT86401319T
Other languages
English (en)
Inventor
L Davis Harold
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Application granted granted Critical
Publication of ATE85861T1 publication Critical patent/ATE85861T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
AT86401319T 1985-06-20 1986-06-17 Niederleistungsadressenpuffer mit aktiver wirkung. ATE85861T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/746,806 US4677593A (en) 1985-06-20 1985-06-20 Low active-power address buffer
EP86401319A EP0206928B1 (de) 1985-06-20 1986-06-17 Niederleistungsadressenpuffer mit aktiver Wirkung

Publications (1)

Publication Number Publication Date
ATE85861T1 true ATE85861T1 (de) 1993-03-15

Family

ID=25002414

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86401319T ATE85861T1 (de) 1985-06-20 1986-06-17 Niederleistungsadressenpuffer mit aktiver wirkung.

Country Status (6)

Country Link
US (1) US4677593A (de)
EP (1) EP0206928B1 (de)
JP (1) JPS6252793A (de)
KR (1) KR940003808B1 (de)
AT (1) ATE85861T1 (de)
DE (1) DE3687766T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800531A (en) * 1986-12-22 1989-01-24 Motorola, Inc. Address buffer circuit for a dram
JPH01256093A (ja) * 1988-04-05 1989-10-12 Matsushita Electric Ind Co Ltd レジスタファイル
JPH03231320A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp マイクロコンピュータシステム
US5016223A (en) * 1990-04-17 1991-05-14 Mitsubishi Denki Kabushiki Kaisha Memory card circuit
US5146111A (en) * 1991-04-10 1992-09-08 International Business Machines Corporation Glitch-proof powered-down on chip receiver with non-overlapping outputs
KR930008838A (ko) * 1991-10-31 1993-05-22 김광호 어드레스 입력 버퍼
US5355032A (en) * 1993-03-24 1994-10-11 Sun Microsystems, Inc. TTL to CMOS translator circuit and method
EP0700051A1 (de) * 1994-08-31 1996-03-06 STMicroelectronics S.r.l. Schaltkreis zum Programmieren einzelner Bits von Worten in einem nichtflüchtigen Speicher
US20070147572A1 (en) * 2005-12-28 2007-06-28 Intel Corporation Registers for an enhanced idle architectural state

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3859637A (en) * 1973-06-28 1975-01-07 Ibm On-chip auxiliary latch for down-powering array latch decoders
US4195238A (en) * 1975-06-04 1980-03-25 Hitachi, Ltd. Address buffer circuit in semiconductor memory
JPS5690483A (en) * 1979-12-19 1981-07-22 Fujitsu Ltd Address buffer circuit
JPS5848292A (ja) * 1981-09-17 1983-03-22 Fujitsu Ltd アドレス・バツフア回路

Also Published As

Publication number Publication date
EP0206928B1 (de) 1993-02-17
JPS6252793A (ja) 1987-03-07
EP0206928A3 (en) 1988-10-05
KR940003808B1 (ko) 1994-05-03
US4677593A (en) 1987-06-30
EP0206928A2 (de) 1986-12-30
DE3687766D1 (de) 1993-03-25
KR870000805A (ko) 1987-02-20
DE3687766T2 (de) 1993-06-09

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties