JPS546760A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS546760A
JPS546760A JP7239877A JP7239877A JPS546760A JP S546760 A JPS546760 A JP S546760A JP 7239877 A JP7239877 A JP 7239877A JP 7239877 A JP7239877 A JP 7239877A JP S546760 A JPS546760 A JP S546760A
Authority
JP
Japan
Prior art keywords
logic circuit
input
fet
diode
interference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7239877A
Other languages
Japanese (ja)
Inventor
Gensuke Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7239877A priority Critical patent/JPS546760A/en
Publication of JPS546760A publication Critical patent/JPS546760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09421—Diode field-effect transistor logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase the logic amplitude and the noise margin by connecting the diode in an opposite polarity to the gate junction with every input circuit connected to the gate terminal of FET, and thus to ensure a high-speed operation as well as a low power consumption in order to avoid the interference between the input.
JP7239877A 1977-06-17 1977-06-17 Logic circuit Pending JPS546760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7239877A JPS546760A (en) 1977-06-17 1977-06-17 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7239877A JPS546760A (en) 1977-06-17 1977-06-17 Logic circuit

Publications (1)

Publication Number Publication Date
JPS546760A true JPS546760A (en) 1979-01-19

Family

ID=13488116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7239877A Pending JPS546760A (en) 1977-06-17 1977-06-17 Logic circuit

Country Status (1)

Country Link
JP (1) JPS546760A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646340A (en) * 1979-09-22 1981-04-27 Nippon Telegr & Teleph Corp <Ntt> Logic circuit using schottky or p-n junction gate type field effect transistor
JPS5741040A (en) * 1980-08-22 1982-03-06 Agency Of Ind Science & Technol Interstage coupling method of electronic circuit
JPS59163858A (en) * 1983-03-09 1984-09-14 Agency Of Ind Science & Technol Gaas logic integrated circuit
JPS6010814A (en) * 1983-06-27 1985-01-21 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション High speed low power logic circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646340A (en) * 1979-09-22 1981-04-27 Nippon Telegr & Teleph Corp <Ntt> Logic circuit using schottky or p-n junction gate type field effect transistor
JPS5741040A (en) * 1980-08-22 1982-03-06 Agency Of Ind Science & Technol Interstage coupling method of electronic circuit
JPS59163858A (en) * 1983-03-09 1984-09-14 Agency Of Ind Science & Technol Gaas logic integrated circuit
JPS6010814A (en) * 1983-06-27 1985-01-21 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション High speed low power logic circuit

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