ATE92211T1 - Programmierbarer kontaktfleck. - Google Patents

Programmierbarer kontaktfleck.

Info

Publication number
ATE92211T1
ATE92211T1 AT87303030T AT87303030T ATE92211T1 AT E92211 T1 ATE92211 T1 AT E92211T1 AT 87303030 T AT87303030 T AT 87303030T AT 87303030 T AT87303030 T AT 87303030T AT E92211 T1 ATE92211 T1 AT E92211T1
Authority
AT
Austria
Prior art keywords
doped region
bonding pad
epitaxial layer
oxide
contact pad
Prior art date
Application number
AT87303030T
Other languages
English (en)
Inventor
Giovanni Piccolo Giannella
Original Assignee
Exar Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exar Corp filed Critical Exar Corp
Application granted granted Critical
Publication of ATE92211T1 publication Critical patent/ATE92211T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
AT87303030T 1986-04-17 1987-04-08 Programmierbarer kontaktfleck. ATE92211T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85330386A 1986-04-17 1986-04-17
EP87303030A EP0243034B1 (de) 1986-04-17 1987-04-08 Programmierbarer Kontaktfleck

Publications (1)

Publication Number Publication Date
ATE92211T1 true ATE92211T1 (de) 1993-08-15

Family

ID=25315668

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87303030T ATE92211T1 (de) 1986-04-17 1987-04-08 Programmierbarer kontaktfleck.

Country Status (4)

Country Link
EP (1) EP0243034B1 (de)
JP (1) JPS6366948A (de)
AT (1) ATE92211T1 (de)
DE (1) DE3786693T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949150A (en) * 1986-04-17 1990-08-14 Exar Corporation Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers
JPH02220442A (ja) * 1989-02-21 1990-09-03 Fuji Electric Co Ltd 半導体装置の保護膜補強構造
US5021856A (en) * 1989-03-15 1991-06-04 Plessey Overseas Limited Universal cell for bipolar NPN and PNP transistors and resistive elements
JP2566684Y2 (ja) * 1991-09-26 1998-03-30 セーレン株式会社 天然セリシン繊維
DE19825608C1 (de) * 1998-06-08 1999-09-23 Siemens Ag Integrierte Halbleiterschaltung mit einer Anschlußfläche, die eine fein abgestufte RC-Charakteristik aufweist
WO2008001248A2 (en) * 2006-06-28 2008-01-03 Nxp B.V. Integrated circuit
US8058674B2 (en) * 2009-10-07 2011-11-15 Moxtek, Inc. Alternate 4-terminal JFET geometry to reduce gate to source capacitance

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573488A (en) * 1967-09-05 1971-04-06 Rca Corp Electrical system and lsi standard cells
JPS607388B2 (ja) * 1978-09-08 1985-02-23 富士通株式会社 半導体記憶装置
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method
JPS60247940A (ja) * 1984-05-23 1985-12-07 Hitachi Ltd 半導体装置およびその製造方法
DE3431632A1 (de) * 1984-08-29 1986-03-06 Philips Patentverwaltung Gmbh, 2000 Hamburg Halbleiterbauelement

Also Published As

Publication number Publication date
EP0243034B1 (de) 1993-07-28
EP0243034A2 (de) 1987-10-28
DE3786693T2 (de) 1994-02-10
DE3786693D1 (de) 1993-09-02
JPS6366948A (ja) 1988-03-25
EP0243034A3 (en) 1988-09-14

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee