AU631709B2 - Bit stack compatible input/output circuits - Google Patents

Bit stack compatible input/output circuits Download PDF

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Publication number
AU631709B2
AU631709B2 AU68557/90A AU6855790A AU631709B2 AU 631709 B2 AU631709 B2 AU 631709B2 AU 68557/90 A AU68557/90 A AU 68557/90A AU 6855790 A AU6855790 A AU 6855790A AU 631709 B2 AU631709 B2 AU 631709B2
Authority
AU
Australia
Prior art keywords
input
circuits
output
subcomponents
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU68557/90A
Other languages
English (en)
Other versions
AU6855790A (en
Inventor
Robert Paul Masleid
Parsotam Trikam Patel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of AU6855790A publication Critical patent/AU6855790A/en
Application granted granted Critical
Publication of AU631709B2 publication Critical patent/AU631709B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AU68557/90A 1990-01-29 1990-12-28 Bit stack compatible input/output circuits Ceased AU631709B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US471892 1990-01-29
US07/471,892 US4988636A (en) 1990-01-29 1990-01-29 Method of making bit stack compatible input/output circuits

Publications (2)

Publication Number Publication Date
AU6855790A AU6855790A (en) 1991-08-01
AU631709B2 true AU631709B2 (en) 1992-12-03

Family

ID=23873400

Family Applications (1)

Application Number Title Priority Date Filing Date
AU68557/90A Ceased AU631709B2 (en) 1990-01-29 1990-12-28 Bit stack compatible input/output circuits

Country Status (9)

Country Link
US (1) US4988636A (2)
EP (1) EP0440332B1 (2)
JP (1) JPH073668B2 (2)
KR (1) KR930006723B1 (2)
CN (1) CN1020245C (2)
AU (1) AU631709B2 (2)
DE (1) DE69128434D1 (2)
MY (1) MY106061A (2)
SG (1) SG44408A1 (2)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69322855T2 (de) * 1993-04-28 1999-05-20 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Modulare integrierte Schaltungsstruktur
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5548747A (en) * 1995-02-10 1996-08-20 International Business Machines Corporation Bit stack wiring channel optimization with fixed macro placement and variable pin placement
US5760428A (en) * 1996-01-25 1998-06-02 Lsi Logic Corporation Variable width low profile gate array input/output architecture
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
US6725439B1 (en) * 1998-01-29 2004-04-20 International Business Machines Corporation Method of automated design and checking for ESD robustness
US6086627A (en) * 1998-01-29 2000-07-11 International Business Machines Corporation Method of automated ESD protection level verification
US6073343A (en) * 1998-12-22 2000-06-13 General Electric Company Method of providing a variable guard ring width between detectors on a substrate
JP4629826B2 (ja) * 2000-02-22 2011-02-09 パナソニック株式会社 半導体集積回路装置
US6879023B1 (en) * 2000-03-22 2005-04-12 Broadcom Corporation Seal ring for integrated circuits
US6550047B1 (en) * 2000-10-02 2003-04-15 Artisan Components, Inc. Semiconductor chip input/output cell design and automated generation methods
FR2817657B1 (fr) * 2000-12-06 2003-09-26 St Microelectronics Sa Circuit integre a couplage par le substrat reduit
US7350160B2 (en) * 2003-06-24 2008-03-25 International Business Machines Corporation Method of displaying a guard ring within an integrated circuit
US7253012B2 (en) * 2004-09-14 2007-08-07 Agere Systems, Inc. Guard ring for improved matching
US7496877B2 (en) * 2005-08-11 2009-02-24 International Business Machines Corporation Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798606A (en) * 1971-12-17 1974-03-19 Ibm Bit partitioned monolithic circuit computer system
US3999214A (en) * 1974-06-26 1976-12-21 Ibm Corporation Wireable planar integrated circuit chip structure
US3968478A (en) * 1974-10-30 1976-07-06 Motorola, Inc. Chip topography for MOS interface circuit
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
DE3177249D1 (de) * 1980-11-24 1991-08-08 Texas Instruments Inc Pseudo-mikroprogrammsteuerung in einem mikroprozessor mit komprimiertem steuerfestwertspeicher und mit bandanordnung von sammelschienen, alu und registern.
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
JPS58137229A (ja) * 1982-02-09 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
EP0160077A1 (en) * 1983-10-31 1985-11-06 Storage Technology Partners Cmos integrated circuit configuration for eliminating latchup
JPH063826B2 (ja) * 1985-04-22 1994-01-12 日本電気株式会社 スタンダ−ドセルの周辺ブロツク配置方法
US4746966A (en) * 1985-10-21 1988-05-24 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
JPS63108733A (ja) * 1986-10-24 1988-05-13 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
CN1020245C (zh) 1993-04-07
JPH073668B2 (ja) 1995-01-18
EP0440332B1 (en) 1997-12-17
DE69128434D1 (de) 1998-01-29
AU6855790A (en) 1991-08-01
MY106061A (en) 1995-03-31
SG44408A1 (en) 1997-12-19
EP0440332A3 (2) 1994-01-19
EP0440332A2 (en) 1991-08-07
KR910015043A (ko) 1991-08-31
KR930006723B1 (ko) 1993-07-23
US4988636A (en) 1991-01-29
JPH03252871A (ja) 1991-11-12
CN1053863A (zh) 1991-08-14

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