BE750761A - Procede de decapage a l'aide d'un masque evitant le risque de decapage marginal - Google Patents

Procede de decapage a l'aide d'un masque evitant le risque de decapage marginal

Info

Publication number
BE750761A
BE750761A BE750761DA BE750761A BE 750761 A BE750761 A BE 750761A BE 750761D A BE750761D A BE 750761DA BE 750761 A BE750761 A BE 750761A
Authority
BE
Belgium
Prior art keywords
scrapping
marginal
risk
stripping process
mask
Prior art date
Application number
Other languages
English (en)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of BE750761A publication Critical patent/BE750761A/fr

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • CCHEMISTRY; METALLURGY
    • C03GLASS; MINERAL OR SLAG WOOL
    • C03CCHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C15/00Surface treatment of glass, not in the form of fibres or filaments, by etching
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/69Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/69Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/40Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/106Masks, special
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/945Special, e.g. metal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/95Multilayer mask including nonradiation sensitive layer

Landscapes

  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Metallurgy (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
BE750761D 1969-05-22 1970-05-21 Procede de decapage a l'aide d'un masque evitant le risque de decapage marginal BE750761A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6907831.A NL157662B (nl) 1969-05-22 1969-05-22 Werkwijze voor het etsen van een oppervlak onder toepassing van een etsmasker, alsmede voorwerpen, verkregen door toepassing van deze werkwijze.

Publications (1)

Publication Number Publication Date
BE750761A true BE750761A (fr) 1970-11-23

Family

ID=19806987

Family Applications (1)

Application Number Title Priority Date Filing Date
BE750761D BE750761A (fr) 1969-05-22 1970-05-21 Procede de decapage a l'aide d'un masque evitant le risque de decapage marginal

Country Status (10)

Country Link
US (1) US3721592A (fr)
JP (1) JPS4843249B1 (fr)
AT (1) AT318004B (fr)
BE (1) BE750761A (fr)
CA (1) CA933019A (fr)
CH (1) CH544159A (fr)
DE (1) DE2024608C3 (fr)
FR (1) FR2048615A5 (fr)
GB (1) GB1311509A (fr)
NL (1) NL157662B (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5313177B2 (fr) * 1973-06-20 1978-05-08
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US3955981A (en) * 1975-01-06 1976-05-11 Zenith Radio Corporation Method of forming electron-transmissive apertures in a color selection mask by photoetching with two resist layers
US4111725A (en) * 1977-05-06 1978-09-05 Bell Telephone Laboratories, Incorporated Selective lift-off technique for fabricating gaas fets
JPS54115085A (en) * 1978-02-28 1979-09-07 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
US4318759A (en) * 1980-07-21 1982-03-09 Data General Corporation Retro-etch process for integrated circuits
DE3035859A1 (de) * 1980-09-23 1982-05-06 Siemens AG, 1000 Berlin und 8000 München Verfahren zur aetztechnischen und/oder galvanischen herstellung von ringzonen in engen bohrungen
EP0092001B1 (fr) * 1982-04-19 1986-10-08 Lovejoy Industries, Inc. Procédé pour le façonnage et l'achèvement d'une pièce d'ouvrage
DE3343704A1 (de) * 1983-12-02 1985-06-13 Siemens AG, 1000 Berlin und 8000 München Verfahren und vorrichtung zum aetzen von lochrasterplatten, insbesondere fuer plasma-kathoden-display
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US4759821A (en) * 1986-08-19 1988-07-26 International Business Machines Corporation Process for preparing a vertically differentiated transistor device
DE3806287A1 (de) * 1988-02-27 1989-09-07 Asea Brown Boveri Aetzverfahren zur strukturierung einer mehrschicht-metallisierung
FR2683944B1 (fr) * 1991-11-14 1994-02-18 Sgs Thomson Microelectronics Sa Procede de gravure d'un sillon profond.
FR2702306B1 (fr) * 1993-03-05 1995-04-14 Alcatel Nv Procédé d'auto-alignement d'un contact métallique sur un substrat de matériau semi-conducteur.
US6361703B1 (en) * 1999-03-04 2002-03-26 Caterpillar Inc. Process for micro-texturing a mold
TWI234819B (en) * 2003-05-06 2005-06-21 Walsin Lihwa Corp Selective etch method for side wall protection and structure formed using the method

Also Published As

Publication number Publication date
CA933019A (en) 1973-09-04
NL157662B (nl) 1978-08-15
US3721592A (en) 1973-03-20
AT318004B (de) 1974-09-25
FR2048615A5 (fr) 1971-03-19
DE2024608C3 (de) 1980-05-29
DE2024608B2 (de) 1979-09-06
CH544159A (de) 1973-11-15
GB1311509A (en) 1973-03-28
DE2024608A1 (de) 1970-11-26
JPS4843249B1 (fr) 1973-12-18
NL6907831A (fr) 1970-11-24

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