BR0109213A - Verificação de adorno de célula de referência automatizada - Google Patents

Verificação de adorno de célula de referência automatizada

Info

Publication number
BR0109213A
BR0109213A BR0109213-8A BR0109213A BR0109213A BR 0109213 A BR0109213 A BR 0109213A BR 0109213 A BR0109213 A BR 0109213A BR 0109213 A BR0109213 A BR 0109213A
Authority
BR
Brazil
Prior art keywords
voltage
logic level
drain
reference cell
current
Prior art date
Application number
BR0109213-8A
Other languages
English (en)
Inventor
Feng Pan
Colin S Bill
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of BR0109213A publication Critical patent/BR0109213A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells

Landscapes

  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

"VERIFICAçãO DE ADORNO DE CéLULA DE REFERêNCIA AUTOMATIZADA". Um circuito e método de verificação de adorno de referência é fornecido para efetuar uma operação de verificação de programa em um transistor de célula de referência em uma malha de células de memória EEPROM Flash. Um ramal de corrente de referência (14) é utilizado para gerar uma corrente de referência que corresponde a uma voltagem de "overdrive" predeterminada da célula de referência a ser programada. Um ramal de corrente de dreno (16) é acoplado ao transistor de célula de referência a ser programada e gera uma corrente de dreno a uma voltagem de portal fixa aplicada em seu portal de controle e a uma voltagem de dreno predeterminada aplicada a seu dreno quando a corrente de dreno está no nível desejado. Um comparador (18) é utilizado para comparar uma voltagem sentida que corresponde à corrente de dreno e uma voltagem de referência que corresponde à corrente de referência. O comparador gera um sinal de saída que está em um nível lógico baixo quando a voltagem sentida é inferior à voltagem de referência e que está em um nível lógico alto quando a voltagem sentida é maior do que a voltagem de referência. Um pulso de programa é aplicado ao transistor de referência cada vez que o comparador gera o nível lógico baixo e termina o pulso de programa quando o comparador gera o nível lógico alto.
BR0109213-8A 2000-03-14 2001-03-12 Verificação de adorno de célula de referência automatizada BR0109213A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/524,897 US6205056B1 (en) 2000-03-14 2000-03-14 Automated reference cell trimming verify
PCT/US2001/007983 WO2001069604A2 (en) 2000-03-14 2001-03-12 Automated reference cell trimming verify

Publications (1)

Publication Number Publication Date
BR0109213A true BR0109213A (pt) 2003-06-03

Family

ID=24091097

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0109213-8A BR0109213A (pt) 2000-03-14 2001-03-12 Verificação de adorno de célula de referência automatizada

Country Status (10)

Country Link
US (1) US6205056B1 (pt)
EP (1) EP1264315B1 (pt)
JP (1) JP2003527725A (pt)
KR (1) KR20030014367A (pt)
CN (1) CN1418365A (pt)
AT (1) ATE249676T1 (pt)
BR (1) BR0109213A (pt)
DE (1) DE60100752T2 (pt)
TW (1) TW519655B (pt)
WO (1) WO2001069604A2 (pt)

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Also Published As

Publication number Publication date
ATE249676T1 (de) 2003-09-15
TW519655B (en) 2003-02-01
US6205056B1 (en) 2001-03-20
WO2001069604A3 (en) 2002-04-11
CN1418365A (zh) 2003-05-14
KR20030014367A (ko) 2003-02-17
WO2001069604A2 (en) 2001-09-20
EP1264315B1 (en) 2003-09-10
JP2003527725A (ja) 2003-09-16
DE60100752D1 (de) 2003-10-16
DE60100752T2 (de) 2004-07-15
EP1264315A2 (en) 2002-12-11

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]