BR9913467A - Processo e sistema para testar uma memória em operação - Google Patents

Processo e sistema para testar uma memória em operação

Info

Publication number
BR9913467A
BR9913467A BR9913467-5A BR9913467A BR9913467A BR 9913467 A BR9913467 A BR 9913467A BR 9913467 A BR9913467 A BR 9913467A BR 9913467 A BR9913467 A BR 9913467A
Authority
BR
Brazil
Prior art keywords
memory
testing
location
memory location
storage unit
Prior art date
Application number
BR9913467-5A
Other languages
English (en)
Inventor
Mikael Lindberg
Stefan Gustafsson
Mats Ernkell
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9913467A publication Critical patent/BR9913467A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Monitoring And Testing Of Exchanges (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

"PROCESSO E SISTEMA PARA TESTAR UMA MEMóRIA EM OPERAçãO". A presente invenção é relativa a um processo e sistema para testar uma memória em operação. Uma unidade de armazenagem é utilizada para liberar temporariamente uma localização de memória na memória, tornando possível verificar esta localização de memória para erros de bit. Dados projetados para a memória a localização de memória selecionada são armazenados na unidade de armazenagem e, em seu lugar, um padrão de teste é escrito na localização de memória para ser testado e lido novamente, tudo em coordenação com a operação normal da memória. Se o padrão lido a partir da localização de teste não casa com o padrão de teste escrito, um alarme é despertado.
BR9913467-5A 1998-08-21 1999-07-02 Processo e sistema para testar uma memória em operação BR9913467A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9802800A SE9802800D0 (sv) 1998-08-21 1998-08-21 Memory supervision
PCT/SE1999/001207 WO2000011678A1 (en) 1998-08-21 1999-07-02 Memory supervision

Publications (1)

Publication Number Publication Date
BR9913467A true BR9913467A (pt) 2001-06-05

Family

ID=20412313

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9913467-5A BR9913467A (pt) 1998-08-21 1999-07-02 Processo e sistema para testar uma memória em operação

Country Status (8)

Country Link
US (1) US6438719B1 (pt)
EP (1) EP1104579B1 (pt)
AU (1) AU4948899A (pt)
BR (1) BR9913467A (pt)
CA (1) CA2340633C (pt)
DE (1) DE69921150T2 (pt)
SE (1) SE9802800D0 (pt)
WO (1) WO2000011678A1 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6922801B2 (en) * 2001-06-01 2005-07-26 International Business Machines Corporation Storage media scanner apparatus and method providing media predictive failure analysis and proactive media surface defect management
US7114106B2 (en) 2002-07-22 2006-09-26 Finisar Corporation Scalable network attached storage (NAS) testing tool
US20040015761A1 (en) * 2002-07-22 2004-01-22 Finisar Corporation Scalable asynchronous I/O testing tool
US20040015762A1 (en) * 2002-07-22 2004-01-22 Finisar Corporation Scalable system testing tools
FR2910145A1 (fr) * 2006-12-18 2008-06-20 St Microelectronics Sa Procede et dispositif pour securiser la lecture d'une memoire.
US8843446B2 (en) 2011-07-04 2014-09-23 Zerto Ltd. Methods and apparatus for time-based dynamically adjusted journaling
DE102018006313A1 (de) * 2018-06-08 2019-12-12 Giesecke+Devrient Mobile Security Gmbh Verfahren mit Safe-Error-Abwehrmaßnahme

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414665A (en) * 1979-11-21 1983-11-08 Nippon Telegraph & Telephone Public Corp. Semiconductor memory device test apparatus
AT367557B (de) * 1980-04-25 1982-07-12 Schrack Elektrizitaets Ag E Schaltungsanordnung zur ueberwachung der funktion von festwert- und/oder schreib-lesespeichern
JPS5856294A (ja) * 1981-09-30 1983-04-02 Hitachi Ltd ランダムアクセスメモリのリ−ドライトチエツク方法
JPS59112494A (ja) * 1982-12-17 1984-06-28 Fuji Electric Co Ltd メモリテスト方式
JPS63175300A (ja) 1987-01-16 1988-07-19 Hitachi Ltd 半導体集積回路装置
GB2222461B (en) * 1988-08-30 1993-05-19 Mitsubishi Electric Corp On chip testing of semiconductor memory devices
JP2779538B2 (ja) * 1989-04-13 1998-07-23 三菱電機株式会社 半導体集積回路メモリのためのテスト信号発生器およびテスト方法
JP2838425B2 (ja) * 1990-01-08 1998-12-16 三菱電機株式会社 半導体記憶装置
US5274648A (en) * 1990-01-24 1993-12-28 International Business Machines Corporation Memory card resident diagnostic testing
EP0470030A3 (en) * 1990-08-02 1993-04-21 International Business Machines Corporation Fast memory power-on diagnostics using direct memory addressing
JP2673395B2 (ja) * 1990-08-29 1997-11-05 三菱電機株式会社 半導体記憶装置およびそのテスト方法
JPH04356799A (ja) * 1990-08-29 1992-12-10 Mitsubishi Electric Corp 半導体記憶装置
DE4028819A1 (de) 1990-09-11 1992-03-12 Siemens Ag Schaltungsanordnung zum testen eines halbleiterspeichers mittels paralleltests mit verschiedenen testbitmustern
US6105152A (en) * 1993-04-13 2000-08-15 Micron Technology, Inc. Devices and methods for testing cell margin of memory devices
US5479413A (en) * 1994-06-06 1995-12-26 Digital Equipment Corporation Method for testing large memory arrays during system initialization
KR0152914B1 (ko) * 1995-04-21 1998-12-01 문정환 반도체 메모리장치
JP3673027B2 (ja) * 1996-09-05 2005-07-20 沖電気工業株式会社 テスト対象の半導体記憶回路を備えた半導体記憶装置
JPH10134599A (ja) * 1996-10-31 1998-05-22 Kawasaki Steel Corp 半導体記憶装置

Also Published As

Publication number Publication date
US6438719B1 (en) 2002-08-20
EP1104579B1 (en) 2004-10-13
WO2000011678A1 (en) 2000-03-02
CA2340633C (en) 2006-11-14
EP1104579A1 (en) 2001-06-06
CA2340633A1 (en) 2000-03-02
SE9802800D0 (sv) 1998-08-21
AU4948899A (en) 2000-03-14
DE69921150T2 (de) 2005-03-17
DE69921150D1 (de) 2004-11-18

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]