BRPI0409247A - arquitetura de ram sìncrona de porta dual virtual - Google Patents

arquitetura de ram sìncrona de porta dual virtual

Info

Publication number
BRPI0409247A
BRPI0409247A BRPI0409247-3A BRPI0409247A BRPI0409247A BR PI0409247 A BRPI0409247 A BR PI0409247A BR PI0409247 A BRPI0409247 A BR PI0409247A BR PI0409247 A BRPI0409247 A BR PI0409247A
Authority
BR
Brazil
Prior art keywords
ram
clock
host
dual port
clock signal
Prior art date
Application number
BRPI0409247-3A
Other languages
English (en)
Inventor
Tao Li
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0409247A publication Critical patent/BRPI0409247A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

"ARQUITETURA DE RAM SìNCRONA DE PORTA DUAL VIRTUAL". São descritos um dispositivo, sistema e método de RAM síncrona de porta dual virtual, nos quais o desenho exige um custo de hardware mínimo comparado com o de uma arquitetura de RAM de porta dual ou o da arquitetura tradicional utilizada com uma RAM de porta única. é descrito um dispositivo de memória de leitura/gravação que inclui meios para aceitar sinais de um primeiro hospedeiro e de um segundo hospedeiro, o primeiro hospedeiro tendo um primeiro relógio e o segundo hospedeiro tendo um segundo relógio, os sinais incluindo um primeiro sinal de relógio e um segundo sinal de relógio, um meio de comutação de relógio para comutar entre o primeiro sinal de relógio e o segundo sinal de relógio, um módulo de memória de acesso aleatório (RAM) para armazenar dados e um relógio de RAM para sincronizar os sinais de relógio com o módulo de RAM.
BRPI0409247-3A 2003-04-11 2004-04-12 arquitetura de ram sìncrona de porta dual virtual BRPI0409247A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US46265303P 2003-04-11 2003-04-11
US10/686,960 US6928027B2 (en) 2003-04-11 2003-10-15 Virtual dual-port synchronous RAM architecture
PCT/US2004/011375 WO2004092966A1 (en) 2003-04-11 2004-04-12 A virtual dual-port synchronous ram architecture

Publications (1)

Publication Number Publication Date
BRPI0409247A true BRPI0409247A (pt) 2006-03-28

Family

ID=33135302

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0409247-3A BRPI0409247A (pt) 2003-04-11 2004-04-12 arquitetura de ram sìncrona de porta dual virtual

Country Status (4)

Country Link
US (1) US6928027B2 (pt)
KR (1) KR100872018B1 (pt)
BR (1) BRPI0409247A (pt)
WO (1) WO2004092966A1 (pt)

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* Cited by examiner, † Cited by third party
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TWI261167B (en) * 2004-12-29 2006-09-01 Via Networking Technologies In Method and related apparatus for realizing two-port synchronous memory device
US8055936B2 (en) * 2008-12-31 2011-11-08 Pitney Bowes Inc. System and method for data recovery in a disabled integrated circuit
US8060453B2 (en) * 2008-12-31 2011-11-15 Pitney Bowes Inc. System and method for funds recovery from an integrated postal security device
US8531907B2 (en) 2011-01-28 2013-09-10 Infineon Technologies Ag Semiconductor memory device and method
US8514652B2 (en) 2011-03-02 2013-08-20 Lsi Corporation Multiple-port memory device comprising single-port memory device with supporting control circuitry
CN103594110B (zh) * 2012-08-15 2017-09-15 上海华虹集成电路有限责任公司 替代双端口静态存储器的存储器结构
CN107844440A (zh) * 2017-10-26 2018-03-27 郑州云海信息技术有限公司 单端口NVMe SSD的访问方法、装置及可读存储介质

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US3715729A (en) 1971-03-10 1973-02-06 Ibm Timing control for a multiprocessor system
US4594657A (en) 1983-04-22 1986-06-10 Motorola, Inc. Semaphore for memory shared by two asynchronous microcomputers
US4597657A (en) * 1983-10-17 1986-07-01 Nippon Kogaku K. K. Compact camera capable of encasing a phototaking optical system
JPS60233741A (ja) * 1984-05-07 1985-11-20 Sony Tektronix Corp デジタル・パタ−ン発生器
US5123107A (en) * 1989-06-20 1992-06-16 Mensch Jr William D Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto
JPH0799831B2 (ja) * 1990-10-08 1995-10-25 株式会社東芝 Ａｔｍ通信システム用単位セルスイッチ
FR2684886B1 (fr) * 1991-12-13 1994-04-01 Salomon Sa Ski a face superieure de largeur variable.
US5274678A (en) * 1991-12-30 1993-12-28 Intel Corporation Clock switching apparatus and method for computer systems
US5614847A (en) * 1992-04-14 1997-03-25 Hitachi, Ltd. Semiconductor integrated circuit device having power reduction mechanism
JPH0612313A (ja) * 1992-06-25 1994-01-21 Matsushita Electric Ind Co Ltd メモリ装置
US5675579A (en) * 1992-12-17 1997-10-07 Tandem Computers Incorporated Method for verifying responses to messages using a barrier message
JPH08221981A (ja) * 1994-12-15 1996-08-30 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH0981449A (ja) * 1995-09-13 1997-03-28 Fujitsu Ltd 擬似デュアルポートメモリ
JP2730530B2 (ja) * 1995-10-31 1998-03-25 日本電気株式会社 半導体集積回路及びその駆動方法
US6141769A (en) * 1996-05-16 2000-10-31 Resilience Corporation Triple modular redundant computer system and associated method
JP3406790B2 (ja) * 1996-11-25 2003-05-12 株式会社東芝 データ転送システム及びデータ転送方法
US5996043A (en) * 1997-06-13 1999-11-30 Micron Technology, Inc. Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US6002882A (en) * 1997-11-03 1999-12-14 Analog Devices, Inc. Bidirectional communication port for digital signal processor
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
US6094727A (en) * 1998-06-23 2000-07-25 Micron Technology, Inc. Method and apparatus for controlling the data rate of a clocking circuit
JP3769940B2 (ja) * 1998-08-06 2006-04-26 株式会社日立製作所 半導体装置
US6650637B1 (en) * 1998-12-14 2003-11-18 Lucent Technologies Inc. Multi-port RAM based cross-connect system
JP2000268559A (ja) * 1999-03-12 2000-09-29 Nec Corp 半導体集積回路装置
WO2001082222A1 (en) * 2000-04-20 2001-11-01 Koninklijke Philips Electronics N.V. Frequency sensor for each interface of a data carrier
JP3815948B2 (ja) * 2000-04-20 2006-08-30 シャープ株式会社 Ｆｉｆｏメモリ制御回路
US6500185B1 (en) * 2000-09-29 2002-12-31 Primus Medical, Inc. Snare device
US7039146B2 (en) * 2001-01-16 2006-05-02 Advanced Micro Devices, Inc. Method and interface for glitch-free clock switching

Also Published As

Publication number Publication date
US20040202040A1 (en) 2004-10-14
KR100872018B1 (ko) 2008-12-05
KR20050119688A (ko) 2005-12-21
WO2004092966A1 (en) 2004-10-28
US6928027B2 (en) 2005-08-09

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Legal Events

Date Code Title Description
B08F Application fees: application dismissed [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2159 DE 22/05/2012.