BRPI0511207A - processo de realização de uma estrutura multicamadas - Google Patents

processo de realização de uma estrutura multicamadas

Info

Publication number
BRPI0511207A
BRPI0511207A BRPI0511207-9A BRPI0511207A BRPI0511207A BR PI0511207 A BRPI0511207 A BR PI0511207A BR PI0511207 A BRPI0511207 A BR PI0511207A BR PI0511207 A BRPI0511207 A BR PI0511207A
Authority
BR
Brazil
Prior art keywords
intermediate layer
layer
impurities
making
initial
Prior art date
Application number
BRPI0511207-9A
Other languages
English (en)
Inventor
Michel Bruel
Original Assignee
Michel Bruel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Michel Bruel filed Critical Michel Bruel
Publication of BRPI0511207A publication Critical patent/BRPI0511207A/pt

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Abstract

PROCESSO DE REALIZAçãO DE UMA ESTRUTURA MULTICAMADAS Processo de realização de uma estrutura multicamadas que comporta, em profundidade, uma camada de separação, que consiste em realizar uma estrutura inicial multicamadas (1) que comporta um substrato de base (2), um substrato de superfície (5) e, entre o substrato de base e o substrato de superfície, uma camada absorvente (3) suscetível de absorver um fluxo de potência luminosa em pelo menos uma área e uma camada intermediária liquidificável (4) que comporta em pelo menos uma área impurezas que apresenta um coeficiente de segregação em relação ao material que constitui essa camada intermediária inferior a um; e em submeter, durante um tempo determinado e sob a forma de pelo menos um impulso, a referida estrutura inicial (1) ao referido fluxo de potência luminosa, fluxo de potência esse que está regulado de modo a produzir a liquefação de pelo menos uma parte da referida camada intermediária (4) sob o efeito da propagação da energia térmica; de modo que resulta, graças A presença inicial das referidas impurezas, uma modificação de pelo menos uma característica e/ou de pelo menos uma propriedade da referida camada intermediária (4) no final da solidificação pelo menos parcial da referida camada intermediária, tal que essa camada intermediária constitua pelo menos parcialmente uma camada de separação.
BRPI0511207-9A 2004-06-01 2005-05-20 processo de realização de uma estrutura multicamadas BRPI0511207A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0405883A FR2870988B1 (fr) 2004-06-01 2004-06-01 Procede de realisation d'une structure multi-couches comportant, en profondeur, une couche de separation
PCT/FR2005/001262 WO2006000669A2 (fr) 2004-06-01 2005-05-20 Procédé de réalisation d'une structure multi-couches comportant, en profondeur, une couche de séparation.

Publications (1)

Publication Number Publication Date
BRPI0511207A true BRPI0511207A (pt) 2007-11-27

Family

ID=34946629

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0511207-9A BRPI0511207A (pt) 2004-06-01 2005-05-20 processo de realização de uma estrutura multicamadas

Country Status (8)

Country Link
US (1) US7846816B2 (pt)
EP (1) EP1774579B1 (pt)
JP (1) JP5335237B2 (pt)
CN (1) CN100444335C (pt)
AU (1) AU2005256723B8 (pt)
BR (1) BRPI0511207A (pt)
FR (1) FR2870988B1 (pt)
WO (1) WO2006000669A2 (pt)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8288684B2 (en) * 2007-05-03 2012-10-16 Electro Scientific Industries, Inc. Laser micro-machining system with post-scan lens deflection
FR2961719B1 (fr) * 2010-06-24 2013-09-27 Soitec Silicon On Insulator Procede de traitement d'une piece en un materiau compose
FR2965396B1 (fr) * 2010-09-29 2013-02-22 S O I Tec Silicon On Insulator Tech Substrat démontable, procédés de fabrication et de démontage d'un tel substrat
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
FR2980279B1 (fr) * 2011-09-20 2013-10-11 Soitec Silicon On Insulator Procede de fabrication d'une structure composite a separer par exfoliation
CN107039532B (zh) * 2012-03-30 2020-08-25 帝人株式会社 掺杂剂注入层、其形成方法及半导体装置的制造方法
FR2991499A1 (fr) * 2012-05-31 2013-12-06 Commissariat Energie Atomique Procede et systeme d'obtention d'une tranche semi-conductrice
CN106340439A (zh) * 2015-07-06 2017-01-18 勤友光电股份有限公司 用于镭射剥离处理的晶圆结构
DE102016000051A1 (de) * 2016-01-05 2017-07-06 Siltectra Gmbh Verfahren und Vorrichtung zum planaren Erzeugen von Modifikationen in Festkörpern
EP4166270B1 (de) * 2016-03-22 2024-10-16 Siltectra GmbH Verfahren zum abtrennen durch laserbestrahlung einer festkörperschicht von einem festkörper
WO2018108938A1 (de) 2016-12-12 2018-06-21 Siltectra Gmbh Verfahren zum dünnen von mit bauteilen versehenen festkörperschichten
TWI631022B (zh) * 2016-12-26 2018-08-01 謙華科技股份有限公司 熱印頭模組之製造方法
FR3079657B1 (fr) * 2018-03-29 2024-03-15 Soitec Silicon On Insulator Structure composite demontable par application d'un flux lumineux, et procede de separation d'une telle structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2506344B2 (fr) * 1980-02-01 1986-07-11 Commissariat Energie Atomique Procede de dopage de semi-conducteurs
US4415373A (en) * 1981-11-17 1983-11-15 Allied Corporation Laser process for gettering defects in semiconductor devices
EP1758169A3 (en) * 1996-08-27 2007-05-23 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same
JP2004140380A (ja) * 1996-08-27 2004-05-13 Seiko Epson Corp 薄膜デバイスの転写方法、及びデバイスの製造方法
JPH1126733A (ja) 1997-07-03 1999-01-29 Seiko Epson Corp 薄膜デバイスの転写方法、薄膜デバイス、薄膜集積回路装置，アクティブマトリクス基板、液晶表示装置および電子機器
EP0926709A3 (en) * 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Method of manufacturing an SOI structure
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP3911929B2 (ja) * 1999-10-25 2007-05-09 セイコーエプソン株式会社 液晶表示装置の製造方法
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
US7211214B2 (en) * 2000-07-18 2007-05-01 Princeton University Laser assisted direct imprint lithography
JP2005510871A (ja) 2001-11-30 2005-04-21 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 半導体装置の製造方法
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
US7105425B1 (en) * 2002-05-16 2006-09-12 Advanced Micro Devices, Inc. Single electron devices formed by laser thermal annealing

Also Published As

Publication number Publication date
EP1774579A2 (fr) 2007-04-18
WO2006000669A2 (fr) 2006-01-05
CN1998071A (zh) 2007-07-11
JP5335237B2 (ja) 2013-11-06
AU2005256723B2 (en) 2011-02-10
US20090053877A1 (en) 2009-02-26
FR2870988A1 (fr) 2005-12-02
CN100444335C (zh) 2008-12-17
WO2006000669A3 (fr) 2007-01-25
AU2005256723A1 (en) 2006-01-05
JP2008501228A (ja) 2008-01-17
AU2005256723B8 (en) 2011-07-28
FR2870988B1 (fr) 2006-08-11
US7846816B2 (en) 2010-12-07
EP1774579B1 (fr) 2012-05-16

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE AS 6A E 7A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2158 DE 15/05/2012.