BRPI0512670A - método de comando para comandar a execução de programa/instrução de computador, e, processador de computador - Google Patents

método de comando para comandar a execução de programa/instrução de computador, e, processador de computador

Info

Publication number
BRPI0512670A
BRPI0512670A BRPI0512670-3A BRPI0512670A BRPI0512670A BR PI0512670 A BRPI0512670 A BR PI0512670A BR PI0512670 A BRPI0512670 A BR PI0512670A BR PI0512670 A BRPI0512670 A BR PI0512670A
Authority
BR
Brazil
Prior art keywords
computer
processor
command
commanding
program
Prior art date
Application number
BRPI0512670-3A
Other languages
English (en)
Inventor
Xiaobo Li
Original Assignee
Xiaobo Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiaobo Li filed Critical Xiaobo Li
Publication of BRPI0512670A publication Critical patent/BRPI0512670A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
  • Programmable Controllers (AREA)

Abstract

MéTODO DE COMANDO PARA COMANDAR A EXECUçãO DE PROGRAMA/INSTRUçãO DE COMPUTADOR, E, PROCESSADOR DE COMPUTADOR A invenção relaciona-se a tecnologia de arquitetura de computador no campo de computador. Mais especificamente, a invenção relaciona-se a um novo método de comando para comandar a execução de programa/instrução de computador, e uma arquitetura de processador de computador e processador de computador usando o método. Como uma das características da invenção, mesmo na condição em que nenhum processo interrupto é envolvido, o processador deste tipo pode executar programas múltiplos em paralelo em um único processador deste tipo, exatamente ao mesmo tempo. Aqui, o processador único relaciona-se a um processador único constituído de uma seção de comando de instrução, uma seção de comando de operação, uma seção de memória de programa, uma seção de memória de dados e uma seção de comunicação. Como uma outra característica da invenção, um comando de execução de programa (PED) é provido para cada um dos programas, e os múltiplos PED podem gerenciar e comandar a execução de programa múltiplos em paralelo no processador único acima, ao mesmo tempo, independentemente ou cooperativamente um com o outro. A invenção é adaptada para projetar vários processadores de computador, tal como um microprocessador de chip único, DSP e CPU de computador com várias escalas.
BRPI0512670-3A 2004-06-28 2005-06-09 método de comando para comandar a execução de programa/instrução de computador, e, processador de computador BRPI0512670A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNB2004100497595A CN100489783C (zh) 2004-06-28 2004-06-28 在单计算机上可在同一时刻执行多道程序的方法及系统
PCT/CN2005/000826 WO2006000145A1 (fr) 2004-06-28 2005-06-09 Procede de commande 'l' destine a commander l'execution d'un programme/instruction et d'une architecture, et processeur associe

Publications (1)

Publication Number Publication Date
BRPI0512670A true BRPI0512670A (pt) 2008-04-01

Family

ID=34665825

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0512670-3A BRPI0512670A (pt) 2004-06-28 2005-06-09 método de comando para comandar a execução de programa/instrução de computador, e, processador de computador

Country Status (8)

Country Link
US (1) US7761877B2 (pt)
EP (1) EP1770516A4 (pt)
JP (1) JP5336076B2 (pt)
KR (1) KR100834180B1 (pt)
CN (1) CN100489783C (pt)
BR (1) BRPI0512670A (pt)
RU (1) RU2007101465A (pt)
WO (1) WO2006000145A1 (pt)

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Publication number Priority date Publication date Assignee Title
CN100514301C (zh) * 2005-03-30 2009-07-15 李晓波 一种程序缓时执行的方法及其装置
CN102236724B (zh) * 2010-04-23 2015-04-01 中山市云创知识产权服务有限公司 最佳均衡器参数计算系统及方法
US20120159341A1 (en) 2010-12-21 2012-06-21 Microsoft Corporation Interactions with contextual and task-based computing environments
US9483324B2 (en) * 2012-06-26 2016-11-01 Nec Corporation Program conversion device and method, process switching method, method of determining execution scheme and program storage medium therefor, processor system, and parallel execution scheme
US9183399B2 (en) * 2013-02-14 2015-11-10 International Business Machines Corporation Instruction set architecture with secure clear instructions for protecting processing unit architected state information
CN103885365B (zh) * 2014-03-24 2018-07-06 三和智控(北京)系统集成有限公司 一种动态管理控制逻辑集的方法
US10740105B2 (en) * 2014-04-04 2020-08-11 Texas Instruments Incorporated Processor subroutine cache
TWI574158B (zh) * 2014-12-01 2017-03-11 旺宏電子股份有限公司 具應用程式資訊感知的資料處理方法以及系統
CN105808338A (zh) * 2016-03-17 2016-07-27 李晓波 一种在处理中实现中断响应核可配置的方法及装置
CN115766675A (zh) * 2022-11-09 2023-03-07 遥在(山东)数字科技有限公司 一种用于vr全景视频的音视频传输方法及系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5522082A (en) 1986-01-23 1996-05-28 Texas Instruments Incorporated Graphics display processor, a graphics display system and a method of processing graphics data with control signals connected to a central processing unit and graphics circuits
JP2908598B2 (ja) * 1991-06-06 1999-06-21 松下電器産業株式会社 情報処理装置
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US5857103A (en) * 1996-06-14 1999-01-05 Sun Microsystems, Inc. Method and apparatus for addressing extended registers on a processor in a computer system
DE19817024A1 (de) * 1998-04-17 1999-10-21 Alcatel Sa Integrierte Schaltung
DE10000960C1 (de) * 2000-01-12 2001-12-20 Infineon Technologies Ag Datenverarbeitungsvorrichtung
US6640322B1 (en) * 2000-03-22 2003-10-28 Sun Microsystems, Inc. Integrated circuit having distributed control and status registers and associated signal routing means
US7096343B1 (en) * 2000-03-30 2006-08-22 Agere Systems Inc. Method and apparatus for splitting packets in multithreaded VLIW processor
US6658551B1 (en) * 2000-03-30 2003-12-02 Agere Systems Inc. Method and apparatus for identifying splittable packets in a multithreaded VLIW processor
US9032404B2 (en) * 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
US7734833B2 (en) * 2005-09-08 2010-06-08 International Business Machines Corporation Method for scheduling operations called by a task on a real-time or non-real time processor

Also Published As

Publication number Publication date
US20080072023A1 (en) 2008-03-20
CN1595359A (zh) 2005-03-16
WO2006000145A1 (fr) 2006-01-05
JP2008504615A (ja) 2008-02-14
JP5336076B2 (ja) 2013-11-06
RU2007101465A (ru) 2008-08-10
CN100489783C (zh) 2009-05-20
KR20070036083A (ko) 2007-04-02
EP1770516A1 (en) 2007-04-04
US7761877B2 (en) 2010-07-20
KR100834180B1 (ko) 2008-05-30
EP1770516A4 (en) 2008-12-10

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 9A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2260 DE 29/04/2014.